CC2420 Datasheet, PDF (38/87 Pages) List of Unclassifed Manufacturers – 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

SmartRF ^® CC2420
Clear Channel Assessment section on
page 49 for details on CCA.
The preamble sequence is started 12
symbol periods after the command strobe.
After the programmable start of frame
delimiter has been transmitted, data is
fetched from the TXFIFO.
A TXFIFO underflow is issued if too few
bytes are written to the TXFIFO.
Transmission is then automatically
stopped. The underflow is indicated in the
TX_UNDERFLOW status bit, which is
returned during each address byte and
each byte written to the TXFIFO. The
underflow bit is only cleared by issuing a
SFLUSHTX command strobe.
The TXFIFO can only contain one data
frame at a given time.
After complete transmission of a data
frame, the TXFIFO is automatically refilled
with the last transmitted frame. Issuing a
new STXON or STXONCCA command
strobe will then cause CC2420 to retransmit
the last frame.
Writing to the TXFIFO after a frame has
been transmitted will cause the TXFIFO to
be automatically flushed before the new
byte is written. The only exception is if a
TXFIFO underflow has occurred, when a
SFLUSHTX command strobe is required.
Buffered receive mode
In buffered receive mode (RX_MODE 0),
the 128 byte RXFIFO, located in CC2420
RAM, is used to buffer data received by
the demodulator. Accessing data in the
RXFIFO is described in the FIFO access
section on page 29.
The FIFO and FIFOP pins are used to
assist the microcontroller in supervising
the RXFIFO. Please note that the FIFO
and FIFOP pins are only related to the
RXFIFO, even if CC2420 is in transmit
mode.
Multiple data frames may be in the
RXFIFO simultaneously, as long as the
total number of bytes does not exceed
128.
See the RXFIFO overflow section on page
31 for details on how a RXFIFO overflow
is detected and signaled.
Un-buffered, serial mode
Un-buffered mode should be used for
evaluation / debugging purposes only.
Buffered mode is recommended for all
applications.
In un-buffered mode, the FIFO and FIFOP
pins are reconfigured as data and data
clock pins. The TXFIFO and RXFIFO
buffers are not used in this mode. A
synchronous data clock is provided by
CC2420 at the FIFOP pin, and the FIFO
pin is used as data input/output. The
FIFOP clock frequency is 250 kHz when
active. This is illustrated in Figure 21.
In
serial
transmit
mode
(MDMCTRL1.TX_MODE=1),
a
synchronisation sequence is inserted at
the start of each frame by hardware, as in
buffered mode. Data is sampled by CC2420
on the positive edge of FIFOP and should
be updated by the microcontroller on the
negative edge of FIFOP. See Figure 21
for an illustration of the timing in serial
transmit mode. The SFD and CCA pins
retain their normal operation also in serial
mode. CC2420 will remain in serial transmit
mode until transmission is turned off
manually.
In
serial
receive
mode
(MDMCTRL1.RX_MODE=1)
byte
synchronisation is still performed by
CC2420. This means that the FIFOP clock
pin will remain idle low until a start of
frame delimiter has been detected.
Chipcon AS SmartRF^® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09
Page 38 of 87