SI5013 Datasheet, PDF (8/24 Pages) List of Unclassifed Manufacturers – OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5013
Table 3. AC Characteristics (Clock and Data)
(V_DD = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Output Clock Rate
f_CLK
Rate Sel = 1
616
—
675
Rate Sel = 0
154
—
158
Output Rise Time—OC-12
t_R
Output Fall Time—OC-12
t_F
Output Clock Duty Cycle—
OC-12/3
Figure 3
Figure 3
—
125
155
—
125
155
47
50
53
Clock to Data Delay
OC-12
OC-3
t_Cr-D
Figure 2
800
4000
840
4100
900
4200
Clock to Data Delay
OC-12
OC-3
t_Cf-D
Figure 2
10
35
60
800
850
1000
Input Return Loss
100 kHz–622 MHz
–15
—
—
Slicing Level Offset¹
V_SLICE SLICE_LVL = 750 mV to 2.25 V –15
—
15
(relative to the internally set
input common mode voltage)
Slicing Level Accuracy
Loss-of-Signal Range²
(peak-to-peak differential)
SLICE_LVL = 750 mV to 2.25 V —
±5
—
V_LOS
LOS_LVL = 1.50 to 2.50 V
0
—
40
Loss-of-Signal Response Time t_LOS
Figure 5 on page 6
8
20
25
Notes:
1. Adjustment voltage (relative to the internally set input common mode voltage) is calculated as follows:
V_SLICE = (SLICE_LVL – 1.50)/50.
2. Adjustment voltage is calculated as follows: V_LOS = (LOS_LVL – 1.50)/25.
Unit
MHz
ps
ps
% of
UI
ps
ps
dB
mV
mV
mV
µs
8
Rev. 1.4