PDM31564 Datasheet, PDF (8/9 Pages) List of Unclassifed Manufacturers – 256 X 16 CMOS 3.3V STATIC RAM

PRELIMINARY
Write Cycle 3 Timing Diagram (UB, LB Controlled)
ADDRESSES
tAS
WE
t_WC
t_AW
t_WP
t_AH
t_CW
CE
t_BW
UB, LB
DOUT
DIN
t_LZCE(1)
t_LZBE(1)
t_HZWE(1)
High Impedance
t_DS
t_DH
Data Stable
PDM31564
AC Electrical Characteristics
Description
-8*
-10*
-12
-15
-20
WRITE Cycle
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Byte pulse width
Address setup time
Address hold from end of write
Write pulse width
Data setup time
Data hold time
Byte disable to output in low Z^{(1, 3, 4)}
Byte enable to output in high Z^{(1, 3, 4)}
Output disable to output in low Z^{(1, 3, 4)}
Output enable to output in high Z^{(1, 3, 4)}
Write disable to output in low Z^{(1,3, 4)}
Write enable to output in high Z^{(1, 3, 4)}
* V_CC = 3.3v +5%
Sym Min. Max Min. Max Min. Max. Min. Max. Min. Max. Unit
t_WC
8 — 10 — 12 — 15 — 20 — ns
t_CW
7 — 8 — 10 — 11 — 13 — ns
t_AW
7 — 8 — 10 — 11 — 13 — ns
t_BW
7 — 8 — 10 — 12 — 13 — ns
t_AS
0 — 0 — 0 — 0 — 0 — ns
t_AH
0 — 0 — 0 — 0 — 0 — ns
t_WP
7 — 8 — 8 — 9 — 10 — ns
t_DS
5 — 6 — 7 — 8 — 9 — ns
t_DH
0 — 0 — 0 — 0 — 0 — ns
t_LZBE 0 — 0 — 0 — 0 — 0 — ns
t_HZBE — 6 — 6 — 7 — 8 — 9 ns
t_LZOE 0 — 0 — 0 — 0 — 0 — ns
t_HZOE — 6 — 6 — 7 — 7 — 8 ns
t_LZWE 0 — 0 — 0 — 0 — 0 — ns
t_HZWE — 6 6 — — 7 — 7 — 9 ns
8
Rev. 1.2 - 3/31/98