HY514400B Datasheet, PDF (8/8 Pages) List of Unclassifed Manufacturers – 1Mx4, Fast Page mode

HY514400B
NOTE
1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of
8 /RAS-only refresh cycles are required.
2. If /RAS=Vss during power-up,the HY514400B could begin an active cycle. This condition results in higher current than
necessary current which is demanded from the power supply during power-up. It is recommended that /RAS and /CAS
track with Vcc during power-up or be held at a valid VIH in other to minimize the power-up current.
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.),and are assumed to be 5ns for all inputs.
4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF.
5. tOFF(max.) and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to
output voltage levels.
6. Either tRCH or tRRH must be satisfied for a read cycle.
7. tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.
8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
9. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.
10.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.
11.tREF(max.)=128ms is applied to SL-parts only.
12.A burst of 1024 CBR refresh cycles must be executed within 16ms (128ms for SL-part) after exiting self refresh.
13.When CAS goes low at the same time, 4bits data are written into the device.
14.These parameters are determined by the earlier falling edge of /CAS.
15.These parameters are determined by the later rising edge of /CAS.
16.tCWL must be satisfied by /CAS for 4bits access cycle.
17.tCP and tCPT are measured when /CAS and is high state.
CAPACITANCE
(TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.)
Symbol
Parameter
Typ.
CIN1
Input Capacitance (A0~A9)
-
CIN2
Input Capacitance (/RAS, /CAS, /WE, /OE)
-
CDQ
Data Input / Output Capacitance (DQ0~DQ3)
-
Max
Unit
5
pF
7
pF
7
pF
1Mx4,FP DRAM
Rev.10 / Jan.97
8