GVT71128D32 Datasheet, PDF (8/13 Pages) List of Unclassifed Manufacturers – 128K X 32 SYNCHRONOUS BURST SRAM

GALVANTECH,
GVT71128D32
128K X 32 SYNCHRONOUS BURST SRAM
AC TEST CONDITIONS FOR 3.3V I/O
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
0V to 3.0V
1.5ns
1.5V
1.5V
See Figures 1 and 2
AC TEST CONDITIONS FOR 2.5V I/O
Input pulse levels
Input slew rate
Output rise and fall times(max)
Input timing reference levels
Output reference levels
Output load
0V to 2.5V
1.0V/ns
1.8ns
1.25V
1.25V
See Figures 3
OUTPUT LOADS FOR 3.3V I/O
DQ
Z₀ = 50 Ω
50Ω
Vt = 1.5V
Fig. 1 OUTPUT LOAD EQUIVALENT
30 pF
3.3v
DQ
351 Ω
317 Ω
5 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
OUTPUT LOADS FOR 2.5V I/O
DQ
Z₀ = 50Ω
50Ω
Vt = 1.25V
Fig. 3 OUTPUT LOAD EQUIVALENT
NOTES
1. All voltages referenced to VSS (GND).
2. Overshoot:
Undershoot:
V_IH ≤ +6.0V for t ≤ ^tKC /2.
V_IL ≤ -2.0V for t ≤ ^tKC /2
3. I_cc is given with no output current. I_cc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig. 2.
7. At any given temperature and voltage condition, ^tKQHZ is less
than ^tKQLZ and ^tOEHZ is less than ^tOELZ.
8. A READ cycle is defined by byte write enables all HIGH or
ADSP# LOW along with chip enables being active for the
required setup and hold times. A WRITE cycle is defined by at
one byte or all byte WRITE per READ/WRITE TRUTH
TABLE.
9. OE# is a “don’t care” when a byte write enable is sampled LOW.
10. This is a synchronous device. All synchronous inputs must meet
specified setup and hold time, except for “don’t care” as defined
in the truth table.
11. AC I/O curves are available upon request.
12. “Device Deselected” means the device is in POWER -DOWN
mode as defined in the truth table. “Device Selected” means the
device is active.
13. Typical values are measured at 3.3V, 25^oC and 20ns cycle time.
14. MODE pin has an internal pull-up and ZZ pin has an internal
pull-down. These two pins exhibit an input leakage current of
+30 µA.
15. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1 or Fig. 3, for 3.3V or 2.5V I/O
respectivel y
November 20, 1999
Rev. 11/9 9
8
Galvantech, Inc. reserves the right to change products or specifications without notice.