GVT71128D32 Datasheet, PDF (5/13 Pages) List of Unclassifed Manufacturers – 128K X 32 SYNCHRONOUS BURST SRAM

GALVANTECH,
GVT71128D32
128K X 32 SYNCHRONOUS BURST SRAM
TRUTH TABLE
OPERATION
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burs t
READ Cycle, Suspend Burs t
READ Cycle, Suspend Burs t
READ Cycle, Suspend Burs t
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADDRESS
USED
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE# CE2# CE2 ADSP # ADSC# ADV# WRITE# OE#
H
X
X
X
L
X
L
X
L
L
X
X
L
H
X
L
X
X
L
X
L
H
L
X
L
H
X
H
L
X
L
L
H
L
X
X
L
L
H
L
X
X
L
L
H
H
L
X
L
L
H
H
L
X
L
L
H
H
L
X
X
X
X
H
H
L
X
X
X
H
H
L
H
X
X
X
H
L
H
X
X
X
H
L
X
X
X
H
H
L
H
X
X
X
H
L
X
X
X
H
H
H
X
X
X
H
H
H
H
X
X
X
H
H
H
X
X
X
H
H
X
X
X
H
H
H
H
X
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
L
X
H
L
X
H
L
H
H
H
L
H
H
H
L
H
H
L
X
L
X
H
L
H
H
H
L
H
H
L
X
L
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Note:
1. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# +
BW1#*BW2#*BW3#*BW4#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals
HIGH.
2. BW1# enables write to DQ1-DQ8. BW2# enables write to DQ9-DQ16. BW3# enables write to DQ17-DQ24. BW4# enables
write to DQ25-DQ32.
3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time
for OE# and staying HIGH throughout the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be
performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for
clarification.
November 20, 1999
Rev. 11/9 9
5
Galvantech, Inc. reserves the right to change products or specifications without notice.