EN29F002N Datasheet, PDF (8/32 Pages) List of Unclassifed Manufacturers – 2 Megabit (256K x 8-bit) Flash Memory

EN29F002 / EN29F002N
Table 5. EN29F002 Command Definitions
Command
Sequence
Read/Reset
Write
Cycles
Req’d
Read/Reset
1
Read/Reset
4
AutoSelect
4
Manufacturer ID
AutoSelect Device ID
4
(Top Boot)
AutoSelect Device ID
4
(Bottom Boot)
AutoSelect Sector
4
Protect Verify
Byte Program
4
Chip Erase
6
Sector Erase
6
Sector Erase Suspend ¹
Sector Erase Resume ¹
1^st
Write Cycle
2^nd
Write Cycle
Addr Data
XXXh F0h
555h AAh
555h AAh
Addr Data
RA RD
AAAh 55h
AAAh 55h
555h AAh AAAh 55h
555h AAh AAAh 55h
555h AAh AAAh 55h
555h AAh AAAh 55h
555h AAh AAAh 55h
555h AAh AAAh 55h
xxxh B0h
xxxh 30h
3^rd
Write Cycle
4^th
Write Cycle
5^th
Write Cycle
6^th
Write Cycle
Addr Data Addr Data Addr Data Addr Data
555h F0h RA RD
555h 90h 000h/ 7Fh/
100h 1Ch
555h 90h 001h/ 7Fh/
101h 92h
555h 90h 001h/ 7Fh/
101h 97h
555h 90h SA & 00h/
02h 01h
555h A0h PA PD
555h 80h 555h AAh AAAh 55h 555h 10h
555h 80h 555h AAh AAAh 55h SA 30h
Notes:
RA = Read Address: address of the memory location to be read. This one is a read cycle.
RD = Read Data: data read from location RA during Read operation. This one is a read cycle.
PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the sector to be erased. Address bits A17-A13 uniquely select any sector.
Byte Programming Command
Programming the EN29F002 is performed on a byte-by-byte basis using a four bus-cycle operation
(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).
When the program command is executed, no additional CPU controls or timings are necessary. The
program operation is terminated automatically by an internal timer. Address is latched on the falling
edge of CE or W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is
first. The program operation is completed when EN29F002 returns the equivalent data to the
programmed location.
Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle
bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is
exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.
EN29F002 ignores commands written during Byte Programming. If a hardware RESET occurs
during Byte Programming, data at the programmed location may get corrupted. Programming is
allowed in any sequence and across any sector boundary.
Chip Erase Command
An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed.
Although the Chip Erase command requires six bus cycles: two unlock write cycles, a setup
command, two additional unlock write cycles and the chip erase command, the user does not need to
do anything else after that, except check to see if the operation has completed. The Auto Chip Erase
algorithm automatically programs and verifies the entire memory array for an all “0” pattern prior to
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