WM8734 Datasheet, PDF (7/42 Pages) List of Unclassifed Manufacturers – STEREO AUDIO CODEC

WM8734
MASTER CLOCK TIMING
MCLK
t _MCLKL
t _MCLKH
t _MCLKY
Advanced Information
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25^oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK System clock pulse width high
TXTIH
MCLK System clock pulse width low
TXTIL
MCLK System clock cycle time
TXTIY
MCLK Duty cycle
TEST CONDITIONS
MIN
18
18
54
40:60
TYP
MAX
UNIT
ns
ns
ns
60:40
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8734
CODEC ^DACLRC
ADCDAT
DACDAT
DSP
ENCODER/
DECODER
Figure 2 Master Mode Connection
w
AI Rev 2.2 November 2001
7