WM8734 Datasheet, PDF (26/42 Pages) List of Unclassifed Manufacturers – STEREO AUDIO CODEC

WM8734
Advanced Information
The exact sample rates achieved are defined by the relationships in Table 11 below.
TARGET
SAMPLING
RATE
KHz
8
ACTUAL SAMPLING RATE
BOSR=0
BOSR=1
(256fs)
(384fs)
MCLK=12.288
MCLK=11.2896
MCLK=18.432
MCLK=16.9344
KHz
KHz
KHz
KHz
8
8.018
8
8.018
12.288MHz/256 x 1/6
11.2896MHz/256 x 2/11
18.432MHz/384 x 1/6
16.9344MHz/384 x 2/11
32
32
not available
32
not available
44.1
12.288MHz/256 x 2/3
not available
44.1
18.432MHz/384x 2/3
not available
44.1
11.2896MHz/256
16.9344MHz /384
48
48
not available
48
not available
88.2
12.288MHz/256
not available
88.2
18.432MHz/384
not available
88.2
11.2896MHz/384 x 2
16.9344MHz /384 x 2
96
96
not available
96
not available
12.288MHz/256 x 2
18.432MHz/384 x 2
Table 11 Normal Mode Actual Sample Rates
128/192fs NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the
WM8734 is also capable of being clocked from a 128 or 192fs MCLK for application over limited
sampling rates as shown in the table below.
SAMPLING
RATE
ADC DAC
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
KHz KHz
MHz
BOSR SR3 SR2 SR1
48
48
6.144
0
0
1
1
9.216
1
0
1
1
44.1 44.1
5.6448
0
1
1
1
8.4672
1
1
1
1
Table 12 128fs Normal Mode Sample Rate Look-up Table
SR0
1
1
1
1
DIGITAL
FILTER
TYPE
2
2
512/768fs NORMAL MODE
512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to
the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384 fs internally and the
device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 6 for
software control.
w
AI Rev 2.2 November 2001
26