NT6868C Datasheet, PDF (7/15 Pages) List of Unclassifed Manufacturers – Keyboard Controller

NT6868C
LED Port
There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C9
LED
-
-
-
-
-
LED2 LED1 LED0 (W)
WREN
DB
RST
L
Q
D _SD
LED [ 0 ]
WREN
DB
RST
L
Q
D _SD
VDD
LED [ 1:2 ]
LED0 Port Structure
LED1, LED2 Port Structures
Watch-Dog Timer
NT6868C implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must
be cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by the software. The user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.
For example:
LDA
STA
#$55
$00CA
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00CA CLRWDT
0
1
0
1
0
1
0
1
(W)
Low Voltage Reset (LVR) Circuit
The NT6868C will check on the voltage level of the power supply. When the voltage level of power supply is below a
threshold of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above a threshold
voltage of 3.0V (Typical) again. As soon as the power voltage reaches 3.0V (Typical), the entire chip will be reset for about
150ms.
RESET
NT6868C can also be externally reset through the RESET pin. A reset is initiated when the signal at the RESET pin is
held LOW for at least 10 system clocks. As soon as the RESET signal goes high, the NT6868C begins to reset for about
150ms. The following shows the definition of the RESET input at LOW pulse width.
V DD
VDD
20%VDD
Trstb
20%VDD
7