NT6868C Datasheet, PDF (5/15 Pages) List of Unclassifed Manufacturers – Keyboard Controller

Timing Generation
This block generates the system timing and control
signal supplied to the CPU and on-chip peripherals.
There are two types of system clock sources: a built-in
RC oscillator or an external ceramic resonator. Both of
them are mask optional and generate a 4MHz system
clock. They also generate 2MHz for the CPU, and 1 MHz
for the base timer. The following shows the relationship
of code type number with oscillation type.
Oscillator
RC OSC
External Resistor
Code Number
1, 5
3, 7
NT6868C
The following table provides the relationship between
the external resistor and the RC OSC frequency. (This is
for reference only)
External Resistor (KΩ )
39
43
47
56
RC OSC Frequency (MHz)
4.7
4.44
4
3.68
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by the CPU. After a
reset, the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any
time. When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a
timer interrupt only if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap
around and begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be
enabled by writing a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.
Base timer structure:
1µs
8-Bit timer
BT7 BT6 BT5 BT4 BT2 BT2 BT1 BT0
TMRINT
BT Pre-loaded Data:
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C0
BT
BT7 BT6 BT5 BT4 BT3 BT2 BT1
BT0
(W)
Timer Control Register:
$00C1 TCON
-
-
-
-
-
-
-
ENBT ^(W)
INT. Controller
When a BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by the
software. Once set by an interrupt source, it remains HIGH unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by a system reset.
When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine. When a BASE
TIMER interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by the software.
Interrupt Control Register:
Addr.
$00C2
Bit
7
CLRIRQX
-
6
5
4
-
-
-
32
-
-
1
0
R/W
- CLRIRQTMR (W)
5