MTL003 Datasheet, PDF (7/64 Pages) List of Unclassifed Manufacturers – SXGA Flat Panel Controller

MYSON
TECHNOLOGY
MTL003
(Rev. 0.95)
3. FUNCTIONAL DESCRIPTION
3.1 Input Processor
General Description
The function of Input Interface is to provide the interface between MTL003 and external input devices. It can
process both non-interlaced and interlaced RGB graphic input, YUV video input, and digital RGB input
compliant with digital LVDS/PanelLink TMDS interface. It also contains the Decimation circuit to scale down
the input image with arbitrary ratios down to 1/32 and the built-in YUV to RGB color space converter.
3.1.1 RGB Input Format
The RGB input port can work in two modes: Single Pixel mode (24 bits) and Double Pixel mode (48 bits). For
Single Pixel mode, only the ports R1IN[7:0], G1IN[7:0], and B1IN[7:0] are internally sampled. For Double
Pixel mode, besides the ports R1IN[7:0], G1IN[7:0], and B1IN[7:0], the ports R2IN[7:0], G2IN[7:0], and
B2IN[7:0] are needed additionally. The R/G/B1IN ports are sampled at the rising edge of the RGB input clock,
and the R/G/B2IN ports are sampled at the falling edge.
3.1.2 TMDS Input Format
The Digital RGB input port works just in the same way as Sec 3.1.1 except that pin “Digital Input Enable
DIEN” is needed.
With a flexible single or double pixel input interface, the supported format is up to true color, including the 18
bit/pixel or 24 bit/pixel in 1 or 2 pixels/clock mode.
3.1.3 YUV Input Format
The YUV input port supports interlaced video data from the most common video decoder ICs like SAA711x.
The 16 bit data bus is shared with the ports R1IN[7:0] and G1IN[7:0]. The 5 bit control signals are shared
with the port R2IN[4:0]. The 16 bit data is sampled at the rising edge of the shared video clock VPCLK when
the shared data enable HREF is active. The supported formats are YUV4:1:1 and YUV4:2:2 with CCIR601
standard.
3.1.4 YUV to RGB Converter
Is used to convert YCbCr format into RGB format. The basic equations are as follows:
R = Y + 1.371(Cr – 128)
G = Y – 0.698(Cr – 128) – 0.336(Cb – 128)
B = Y + 1.732(Cb - 128)
3.1.5 De-interlace mode
For interlace input, MTL003 features several de-interlacing algorithms for processing interlaced video data
depending on the type of input images.
¨ Static Mode
In this mode, the first and second fields are put together without any filtering. Memory for two fields is
needed. It is commonly used in still image input.
¨ Toggle Mode
In this mode, only one field is displayed at a time. First field and second field is toggled displayed. The
missing lines are calculated from duplicating the neighboring lines. For moving picture, it has a good quality.
¨ Spatial Mode
In this mode, two fields are toggled displayed, just like Toggle mode. The missing lines are calculated from
interpolating the neighboring lines. This mode has an generally good quality for still and moving pictures.
3.1.6 Sync Processor
The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC
inputs the presence check, frequency counting, polarity detection and control. It contains a de-glitch circuit to
filter out any pulse shorter than one OSC period which is treated as noise among V/H SYNC pulses.
Revision 0.95
-7-
2000/06/14