MTD516 Datasheet, PDF (7/27 Pages) List of Unclassifed Manufacturers – 16 Port 10M/100M Ethernet Switch

MYSON
TECHNOLOGY
MTD516
(Preliminary)
Synchronous DRAM/GRAM Interface Pins
Name
AD[8:0]
Pin Number I/O
Descriptions
O Memory row/column address bus outputs
123~131
AD[7:0] are row/column address [7:0].
AD[8] : This pin should connect to SGRAM/SDRAM MSB address bit.
DQ[63:0]
119~112, ^{I/O Memory data bus DQ[63:56] : 119~112}
84~91,
111~108,
DQ[55:48] : 84~91
DQ[47:44] : 111~108
105~102,
DQ[43:40] : 105~102
92~93,
DQ[39:38] : 92~93
96~101,
DQ[37:32] : 96~101
172~165,
DQ[31:24] : 172~165
137~139,
DQ[23:21] : 137~139
142~146,
DQ[20:16] : 142~146
164~161,
DQ[15:12] : 164~161
158~155,
DQ[11:8] : 158~155
147~154
DQ[7:0] : 147~154
RASB
134
O SGRAM/SDRAM row address select
CASB
135
O SGRAM/SDRAM column address select
WEB
136
O SGRAM/SDRAM write enable
BA
132
O SGRAM/SDRAM bank select
CS0B
133
O Memory chip select 0
MEMCLK
121
O Memory clock output.
Note: SGRAM/SDRAM access time: 10 ns (max)
Name
RESETB
SYSCLK
REFCLK
MDC
MDIO
EECLK/
SDC
EEDATA/
SDIO
LEDCLK
Miscellaneous Pins
Pin Number
180
82
178
181
182
176
175
174
I/O
Descriptions
I System reset input, low active.
I Switch core system clock input
I RMII reference clock input
I/O MII management clock inout.
I/O MII management data inout
I/O After ResetB deassert to ? ms , this pin indicate EECLK,
After 150 ms, it indicate SDC.
I/O After ResetB deassert to ? ms , this pin be indicated EEDATA,
After 150 ms, it indicate SDIO.
I/O LED Clock.
Using bursted clock for latching 32 display informations (one clock
latch one information) , per burst have 32 continuous clocks (clock
period = 320 ns); and the time between burst to burst is 655 us.
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MTD516 Revision 1.2 19/06/2000