MTD516 Datasheet, PDF (4/27 Pages) List of Unclassifed Manufacturers – 16 Port 10M/100M Ethernet Switch

MYSON
TECHNOLOGY
MTD516
(Preliminary)
2.0 PIN DESCRIPTIONS
RMII Port Interface Pins
Name
CRSDV0
RXD0_0
RXD0_1
TXEN0
TXD0_0
TXD0_1
CRSDV1
RXD1_0
RXD1_1
TXEN1
TXD1_0
TXD1_1
CRSDV2
RXD2_0
RXD2_1
TXEN2
TXD2_0
TXD2_1
CRSDV3
RXD3_0
RXD3_1
TXEN3
TXD3_0
TXD3_1
CRSDV4
RXD4_0
RXD4_1
TXEN4
TXD4_0
TXD4_1
CRSDV5
RXD5_0
RXD5_1
TXEN5
TXD5_0
TXD5_1
Pin Number
186
187
188
185
184
183
194
195
196
193
192
191
200
201
202
199
198
197
206
207
208
205
204
203
4
5
6
3
2
1
12
13
14
9
8
7
I/O
Descriptions
I Port0 RMII receive interface signal, CRSDV0 is asserted high when
port0 media is non_idle.
I Port0 RMII receive data bit_0.
I Port0 RMII receive data bit_1.
O Port0 RMII transmit enable signal.
O Port0 RMII transmit data bit_0.
O Port0 RMII transmit data bit_1.
I Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
I Port1 RMII receive data bit_0.
I Port1 RMII receive data bit_1.
O Port1 RMII transmit enable signal.
O Port1 RMII transmit data bit_0.
O Port1 RMII transmit data bit_1.
I Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
I Port2 RMII receive data bit_0.
I Port2 RMII receive data bit_1.
O Port2 RMII transmit enable signal.
O Port2 RMII transmit data bit_0.
O Port2 RMII transmit data bit_1.
I Port3 RMII receive interface signal, CRSDV0 is asserted high when
port3 media is non_idle.
I Port3 RMII receive data bit_0.
I Port3 RMII receive data bit_1.
O Port3 RMII transmit enable signal.
O Port3 RMII transmit data bit_0.
O Port3 RMII transmit data bit_1.
I Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
I Port4 RMII/MII receive data bit_0.
I Port4 RMII/MII receive data bit_1.
O Port4 RMII transmit enable signal
O Port4 RMII/MII transmit data bit_0.
O Port4 RMII/MII transmit data bit_1.
I Port5 RMII receive interface signal, CRSDV5 is asserted high when
port5 media is non_idle.
I Port5 RMII receive data bit_0.
I Port5 RMII receive data bit_1.
O Port5 RMII transmit enable signal.
O Port5 RMII transmit data bit_0.
O Port5 RMII transmit data bit_1.
4/27
MTD516 Revision 1.2 19/06/2000