GS71116ATP Datasheet, PDF (7/16 Pages) List of Unclassifed Manufacturers – 1Mb Asynchronous SRAM

GS71116ATP/J/U
AC Characteristics
Read Cycle
Parameter
Symbol
Read cycle time
tRC
Address access time
tAA
Chip enable access time (CE)
tAC
Byte enable access time (UB, LB)
tAB
Output enable to output valid (OE)
tOE
Output hold from address change
tOH
Chip enable to output in low Z (CE)
tLZ^*
Output enable to output in low Z (OE)
tOLZ^*
Byte enable to output in low Z (UB, LB)
tBLZ^*
Chip disable to output in High Z (CE)
tHZ^*
Output disable to output in High Z (OE)
tOHZ^*
Byte disable to output in High Z (UB, LB)
tBHZ^*
* These parameters are sampled and are not 100% tested.
-7
-8
-10
-12
Unit
Min Max Min Max Min Max Min Max
7 — 8 — 10 — 12 — ns
— 7 — 8 — 10 — 12 ns
— 7 — 8 — 10 — 12 ns
— 3 — 3.5 —
4
—
5
ns
— 3 — 3.5 —
4
—
5
ns
3—3—3
—
3
— ns
3—3—3
—
3
— ns
0—0—0
—
0
— ns
0—0—0
—
0
— ns
— 3.5 — 4 —
5
—
6
ns
— 3 — 3.5 —
4
—
5
ns
— 3 — 3.5 — 3.5 — 3.5 —
Read Cycle 1: CE = OE = V_IL, WE = V_IH, UB and, or LB = V_IL
Address
Data Out
tOH
Previous Data
tRC
tAA
Data valid
Rev: 1.07 12/2004
7/16
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology