GS71116ATP Datasheet, PDF (1/16 Pages) List of Unclassifed Manufacturers – 1Mb Asynchronous SRAM

GS71116ATP/J/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
64K x 16
1Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V V_DD
Center V_DD and V_SS
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
GP: Pb-Free 400 mil, 3244-pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: Pb-Free 6 mm x 8 mm Fine Pitch Ball Grid Array
package
• Pb-Free TSOP-II and FP-BGA packages available
Description
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 400 mil SOJ and 400
mil TSOP Type-II packages.
Pin Descriptions
Symbol
A0–A15
DQ1–DQ16
CE
LB
UB
WE
OE
V_DD
V_SS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
SOJ 64K x 16-Pin Configuration
A4
1
A3
2
A2
3
A1
4
A0
5
Top view
CE
6
DQ1
7
DQ2
8
DQ3
9
DQ4
10
V_DD
11
44-pin
V_SS
12
DQ5
13
SOJ
DQ6
14
DQ7
15
DQ8
16
WE
17
A15
18
A14
19
A13
20
A12
21
NC
22
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
DQ16
37
DQ15
36
DQ14
35
DQ13
34
V_SS
33
V_DD
32
DQ12
31
DQ11
30
DQ10
29
DQ9
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Package J
Rev: 1.07 12/2004
1/16
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology