GLT5640L32 Datasheet, PDF (7/49 Pages) List of Unclassifed Manufacturers – CMOS Synchronous DRAM 2M x 32 SDRAM

G-LINK
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
DC CHARACTERISTICS (DC Operating Conditions Unless Otherwise Noted)
PARAMETER
Operating Current
Precharge Standby Current
in Power-down Mode
Precharge Standby Current
in Non Power-down Mode
Active Standby Current in
Power-down Mode
Active Standby Current in
Non Power-down Mode
Operating Current
(Burst Mode)
Operating Current
Self Refresh Current
Notice :
SYM.
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
IDD5
IDD6
TEST CONDITION
BURST Length = 1, One Bank Active
tRAS ≥ tRAS(min), tRP ≥ tRP(min)
IOL = 0 mA
SPEED
UNIT NOTE
5 -5.5 -6 -7 -8 -10
230 220 200 1800 170 150 mA
1
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK=
2
mA
-
2
mA
-
CKE ≥ VIH(min), CS ≥ VIH(min), tCK= 15ns
Input signals are changed on time during 2CKLS
30
All this pins ≥ VDD - 0.2 or ≤ 0.2V
mA
-
CKE ≥ VIH(min), tCK=
Input signals are stable
CKE ≥ VIL(max), tCK = 15ns
20
mA
-
15
mA
-
CKE ≥ VIL(max), tCK=
15
mA
-
CKE ≥ VIH(min), CS ≥ VIH(min), tCK=15ns
Input signals are changed on time during 2CLKS
60
All other pin ≥ VDD - 0.2V or ≤ 0.2V
mA
-
CKE ≥ VIH(min), tCK=
Input signals are stable
50
mA
-
tCK ≥ tCK(min)
tRAS ≥ tRAS(min), IOL = 0 mA
All Bank Active
CL=3 440 410 380 340 300 250
mA
1
CL=2 - - - - 250 200
tRRC ≥ tRRC(min) All banks active
250 240 220 200 190 180 mA
2
CKE ≤ 0.2V
2
mA
3
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. GLT5640L32-5/5.5/6/7/8/10
G-Link Technology Corp.
7
Dec 2003 Rev.0.3