GLT5640L32 Datasheet, PDF (26/49 Pages) List of Unclassifed Manufacturers – CMOS Synchronous DRAM 2M x 32 SDRAM

G-LINK
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the
WRITE command, and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, AUTO
PRECHARGE is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no
other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A full-page burst
will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be
immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous
CLK
CKE
HIGH
CS#
RAS#
T0
T1
T2
T3
CLK
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CAS#
DQ
Din
Din
n
n+1
WE#
A0 - A7
COLUMN
ADDRESS
Notice : Burst length = 2. DQM is LOW
Figure 14.
WRITE Burst
A8, A9
A10
BA0, 1
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
Figure 13.
WRITE Command
T0
T1
CLK
COMMAND
WRITE
NOP
T2
WRITE
ADDRESS
BANK,
COL n
DQ
Din
Din
n
n+1
BANK,
COL b
Din
b
Notice : DQM is LOW. Each WRITE command may be to
any bank
DON’T CARE
Figure 15.
WRITE to WRITE
WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15.
Data n + 1 is either the last of a burst of two or the last desired of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each
subsequent WRITE may be performed to a different bank.
G-Link Technology Corp.
26
Dec 2003 Rev.0.3