VMX1C1020 Datasheet, PDF (68/80 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 Mixed-Signal MCU

VMX51C1020
Interrupt Status Flags
The IRCON register is used to identify the
source of an interrupt. Before exitingthe
interrupt service routine, the IRCON register bit
that corresponds with the serviced interrupt
should be cleared.
TABLE 117: (IRCON) INTERRUPT REQUEST CONTROL REGISTER - SFR 91H
7
6
5
4
T2EXIF
T2IF
ADCIF
MACIF
3
I2CIF
2
SPIRXIF
1
SPITXIF
0
Reserved
Bit Mnemonic
7
T2EXIF
6
T2IF
5
ADCIF /
COMPINT3
4
MACIF /
COMPINT2
3
I2CIF /
COMPINT1
2
SPIRXIF /
COMPINT0
1
SPITXIF
0
Reserved
Function
Timer 2 external reload flag
This bit informs the user
whether an interrupt has been
generated from T2EX, if the
T2EXIE is enabled.
Timer 2 interrupt flag
A/D converter interrupt request
flag/ port 0 change.
/ COMPINT3
MULT/ACCU unit interrupt
request flag / COMPINT2
I²C interrupt request flag
/ COMPINT1
RX available flag SPI + RX
Overrun / / COMPINT0
TX empty flag SPI
Reserved
Interrupt Priority Register
All of the VMX51C1020’s interrupt sources are
combined into groups with four levels of priority.
These groups can be programmed individually
to one of the four priority levels: from Level0 to
Level3 with Level3 being the highest priority.
The IP0 and IP1 registers serve to define the
specific priority of each of the interrupt groups.
By default, when the IP0 and IP1 registers are at
reset state 00h, the natural priority order of the
interrupts shown previously are in force.
TABLE 118: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H
7
6
54 3 2 1 0
UF8 WDTSTAT
IP0 [5:0]
Bit Mnemonic Function
7
UF8
User Flag bit
6
WDTSTAT Watchdog timer status flag. Set to 1
by hardware when the watchdog
timer overflows. Must be cleared
manually
5
IP0.5
Timer 2
Port1
Change
ADC
4
IP0.4
UART0
-
MULT/ACCU
3
IP0.3
Timer 1
-
I2C
2
IP0.2
External
INT1
-
SPI RX
available
1
IP0.1
Timer 0
Interrupt
-
SPI TX
Empty
0
IP0.0
External
INT0
UART1
External
INT 0
Table 119: (IP1) Interrupt Priority Register 1 - SFR B9h
7
6
5
4
3
2
1
0
-
-
IP1 [5:0]
Bit
Mnemonic Function
7
-
-
6
-
-
5
IP1.5
Timer 2
Port1
Change
ADC
4
IP1.4
UART0
-
MULT/ACCU
3
IP1.3
Timer 1
-
I2C
2
IP1.2
External
INT1
-
SPI RX
available
1
IP1.1
Timer 0
Interrupt
-
SPI TX
Empty
0
IP1.0
External
INT0
UART1
External
INT 0
Configuring the IP0 and IP1 registers makes it
possible to change the priority order of the
peripheral interrupts in order give higher priority
to a given interrupt that belongs to a given
group.
TABLE 120: INTERRUPT GROUPS
Bit
Interrupt Group
IP1.5, IP0.5
Timer 2
Port1
Change
IP1.4, IP0.4
UART0
-
IP1.3, IP0.3
Timer 1
-
IP1.2, IP0.2
External
INT1
-
IP1.1, IP0.1
Timer 0
Interrupt
-
IP1.0, IP0.0
External
INT0
UART1
ADC
MULT/ACCU
I2C
SPI RX
available
SPI TX
Empty
External
INT 0
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