VMX1C1020 Datasheet, PDF (54/80 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 Mixed-Signal MCU

VMX51C1020
I²C Interface Interrupts
The I²C interface has a dedicated interrupt
vector located at address 0x5B. Three flags
(see below) share the I²C interrupt vector and
can be used to monitor the I²C interface status
making it possible to activate the I²C interrupt.
I2CTXEMP:
I2CRXAV:
I2CRXOV:
Is set to 1 when the transmit buffer is
empty
Is set to 1 when data byte reception
completes.
Is set to 1 if a new byte reception
completes before the previous data in
the reception buffer is read, resulting in
a data collision.
These flags can all trigger the I²C interrupt if
their corresponding bit in the I2CCONFIG
register is set to one.
In the case where more than one of these flags
can activate an I²C interrupt, the interrupt
service routine is left to figure out which
condition generated the interrupt.
Note that the I2CRXAV, I2CTXEMP and
I2CRXOV flags can still be polled if their
corresponding interrupt enable flag is cleared.
Therefore they can still be used to monitor
status.
Master I²C Operation
In Master mode, the VMX51C1020 I²C interface
controls the I²C bus transfers. In order to
configure the I²C interface as a Master, the
I2CMASTER bit of the I2CCONFIG register
must be set to one.
Once the I²C interface is configured, sending
data to a Slave device connected to the bus is
done by writing the data into the I2CRXTX
register.
Before sending data to a Slave device, a byte
containing the target device’s chip ID and
Read/Write bit must be sent to it.
A master mode data read is triggered by reading
the I2CRXAV (bit 1) of the I2CIRQSTAT
register. The data is present on the I2CRXTX
register when the I2CRXAV bit is set.
Reading the value of the I2CRXTX register
resets the I2CRXAV bit. Once started, the I²C
byte read process will continue until the Master
generates a STOP condition.
When the I²C interface is configured as a
Master, setting the I2CMSTOP bit of the
I2CCONFIG register to a 1 will result in the I²C
interface generating a STOP condition after the
reception of the next byte.
In Master Mode, it’s possible to manually control
the operation of the acknowledged timing when
receiving data. To do this, you must first set the
I2CMANACK bit of the I2CCONFIG register to 1.
Then, once you have received a byte, you can
manually control the acknowledge level by
clearing or setting the I2CMANACK bit.
Note: The VMX51C1020 I²C Interface is not
compatible with the I²C multi-master
mode.
Slave I²C Operation
The VMX51C1020 I²C interface can be
configured as a Slave by clearing the
I2CMASTER bit of the I2CCONFIG register.
In Slave mode, the VMX51C1020 has no control
over the rate or timing of the data exchange that
occurs on the I²C bus. Therefore, in Slave
mode, it is preferable to manage the
transactions using the I²C interrupts.
The I2CMASKID bit, when set, will configure the
Slave device to mask the received ID byte and
receive the data directly. This is useful when
only two devices are present on the I²C bus.
Note:
When the VMX51C1020 starts
transmitting data in Slave mode, it will
continually transmit the value present in
the I²C transmit register as long as the
Master provides the clock signal or until
the Master device generates a STOP
condition
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