RXM-900-HP3 Datasheet, PDF (6/13 Pages) List of Unclassifed Manufacturers – HP3 SERIES RECEIVER MODULE DATA

CHANNEL SELECTION
Parallel Selection
CS2 CS1 CS0 Channel
Frequency
0
0
0
0
All HP3 receiver models feature eight _{0 0 1}
1
903.37
906.37
parallel selectable channels. Parallel ^{0 1 0}
2
Mode is selected by grounding the
0
1
1
0
1
0
3
4
MODE line. In this mode, channel 1 0 1
5
907.87
909.37
912.37
915.37
selection is determined by the logic ^{1 1 0}
6
919.87
states of pins CS0, CS1, and CS2, as ¹
1
1
7
921.37
shown in the adjacent table. A ‘0’ ^{Table 2: Parallel Channel Selection Table}
represents ground and a ‘1’ the positive supply. The on-board microprocessor
performs all PLL loading functions, eliminating external programming and
allowing channel selection via DIP switches or a product’s processor.
Serial Selection
In addition to the Parallel Mode, PS versions of the HP3 also feature 100 serially
selectable channels. The Serial Mode is entered when the MODE line is left open
or held high. In this condition, CS1 and CS2 become a synchronous serial port,
with CS1 serving as the clock line and CS2 as the data line. The module is easily
programmed by sending and latching the binary number (0 to 100) of the desired
channel (see the adjacent Serial Channel Selection Table). With no additional
effort, the module’s microprocessor handles the complex PLL loading functions.
The Serial Mode is
straightforward; however,
minimum timings and bit
order must be followed.
Loading is initiated by
taking the clock line high
and the data line low as
shown. The eight-bit
channel number is then
clocked-in one bit at a
time, with the LSB first.
Note 2
Data
Variable Data
Note 1
Clock
T0
12345678
1ms
T3
T1
25µs
T2 ^8µs
5µs
Note 3
T4
5µs
1) Loading begins when clock line is high and data line is taken low
2) Ensure that edge is fully risen prior to high-clock transition
3) Both lines high triggers automatic latch
(T0) Time between packets or prior to data startup ................................1mS min.
(T1) Data-LO / Clock-HI to Data-LO / Clock-LO .......................................25µS min.
(T2) Clock-LO to Clock-HI ...........................................................................5µS min.
(T3) Clock-HI to Clock-LO ...........................................................................8µS min.
(T4) Data-HI / Clock-HI .................................................................................5µS min.
Total Packet Time ......................................................................................157µS min.
Figure 13: PLL Serial Data Timing
There is no maximum time for this process, only the minimum times that must be
observed. After the eighth bit, both the clock and data lines should be taken high
to trigger the automatic data latch. A typical software routine can complete the
loading sequence in under 200uS. Sample code is available on the Linx website.
NOTE: When the module is powered up in the Serial Mode, it will default to channel 50 until changed
by user software. This allows testing apart from external programming and prevents out-of-band
operation. When programmed properly, the dwell time on this default channel can be less than 200uS.
Channel 50 is not counted as a usable channel since data errors may occur as transmitters also default
to channel 50 on startup. If a loading error occurs, such as a channel number >100 or a timing problem,
the receiver will default to serial channel 0. This is useful for debugging as it verifies serial port activity.
Page 10
SERIAL CHANNEL SELECTION TABLE
CHANNEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50*
TX FREQUENCY
902.62
902.87
903.12
903.37
903.62
903.87
904.12
904.37
904.62
904.87
905.12
905.37
905.62
905.87
906.12
906.37
906.62
906.87
907.12
907.37
907.62
907.87
908.12
908.37
908.62
908.87
909.12
909.37
909.62
909.87
910.12
910.37
910.62
910.87
911.12
911.37
911.62
911.87
912.12
912.37
912.62
912.87
913.12
913.37
913.62
913.87
914.12
914.37
914.62
914.87
915.12
RX LO
867.92
868.17
868.42
868.67
868.92
869.17
869.42
869.67
869.92
870.17
870.42
870.67
870.92
871.17
871.42
871.67
871.92
872.17
872.42
872.67
872.92
873.17
873.42
873.67
873.92
874.17
874.42
874.67
874.92
875.17
875.42
875.67
875.92
876.17
876.42
876.67
876.92
877.17
877.42
877.67
877.92
878.17
878.42
878.67
878.92
879.17
879.42
879.67
879.92
880.17
880.42
CHANNEL TX FREQUENCY
RX LO
51
915.37
880.67
52
915.62
880.92
53
915.87
881.17
54
916.12
881.42
55
916.37
881.67
56
916.62
881.92
57
916.87
882.17
58
917.12
882.42
59
917.37
882.67
60
917.62
882.92
61
917.87
883.17
62
918.12
883.42
63
918.37
883.67
64
918.62
883.92
65
918.87
884.17
66
919.12
884.42
67
919.37
884.67
68
919.62
884.92
69
919.87
885.17
70
920.12
885.42
71
920.37
885.67
72
920.62
885.92
73
920.87
886.17
74
921.12
886.42
75
921.37
886.67
76
921.62
886.92
77
921.87
887.17
78
922.12
887.42
79
922.37
887.67
80
922.62
887.92
81
922.87
888.17
82
923.12
888.42
83
923.37
888.67
84
923.62
888.92
85
923.87
889.17
86
924.12
889.42
87
924.37
889.67
88
924.62
889.92
89
924.87
890.17
90
925.12
890.42
91
925.37
890.67
92
925.62
890.92
93
925.87
891.17
94
926.12
891.42
95
926.37
891.67
96
926.62
891.92
97
926.87
892.17
98
927.12
892.42
99
927.37
892.67
100
927.62
892.92
= Also available in Parallel Mode
*See NOTE on previous page.
Page 11