PE12316 Datasheet, PDF (6/29 Pages) List of Unclassifed Manufacturers – Triple Incremental Encoder

February 6, 2003 Preliminary (Version 1.1)
PE12316
Triple
Incremental Encoder
Detailed Information about the different Modes:
Mode 0: 16-Bit Up/Down Counter Mode
In this mode the PE12316 may be used as three
fast 16-bit synchronous up/down counters with
cascade capability. This is operated using the
/UP and /DOWN inputs.
/A0 is the control input for the byte multiplexer. A
high level at this input transfers the least
significant byte to the data outputs; and a low
level transfers the most significant byte.
The states of the counter outputs are transferred
to a 16-bit latch. The contents of this 16-bit latch
are multiplexed on a 8-bit parallel data bus
(D0…D7) and enabled using /RD and /CS.
The signals /A1 and /A2 select the channel for
read or write according to the following table.
Channel number
/A1
/A2
1
H
H
2
L
H
3
H
L
No channel selected¹
L
L
Table 2 Channel Selection
1_{Output buffers still selected if /RD and /CS active – data bus carries invalid data}
The up/down counters are loaded in individual 8-
bit bytes by the /WR and /CS signals, with the
byte selected by the /A0 input, and the channel
by the /A1 and /A2 inputs.
The counters and the control logic may be
cleared all together using the /RESET signal.
The counters are cleared individually using the
/Ua0n signals.
Cascading to 32, 40, 48 or 56 bits is possible by
connecting the /CARRY, /BORROW outputs of
channel n with the /UP, /DOWN Inputs of the
channel n+1. In cascaded mode the according
/KLI-KLOn have to be connected together. For
further details see Application Notes.
Memory Map:
/A3 /A2 /A1 /A0 Channel
1*
1
1* 1 1 0 Channel 1
0
1
1*
1
1* 1 0 0 Channel 2
0
1
1*
1
1* 0 1 0 Channel 3
0
1
* Defaultvalue due to internal pullup
Content
Bits 0-7
Bits 8-15
Bits 16-23
Bits 0-7
Bits 8-15
Bits 16-23
Bits 0-7
Bits 8-15
Bits 16-23
Table 3 Memory Map
February 6, 2003 (Preliminary Version 1.1)
Page 6/29
PE12316