ICS87608I Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS87608I
LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
10
38
50
7
Units
MHz
Ω
pF
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, V_DD = V_DDA = V_DDOX = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_REF
Reference Frequency
8.33
41.67 MHz
TABLE 7A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDOX = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1
FREF = 25MHz
166.67 MHz
0
160
325
ps
tsk(b) Bank Skew; NOTE 2, 6
60
ps
tsk(o) Output Skew; NOTE 3, 6
250
ps
tjit(cc) Cycle-to-Cycle Jitter; 6
120
ps
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7
20
ps
tsl(o) Slew Rate
1
4
v/ns
t
PLL Lock Time
L
10
ms
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
20% to 80%
200
48
700
ps
52
%
All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the
PLL is locked and the input reference frequency is stable. Measured at V_DD/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDOX/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_IN. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: This parameter is defined as an RMS value.
TABLE 7B. AC CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
V
DDOX
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
f_MAX
t(Ø)
tsk(b)
tsk(o)
tjit(cc)
Output Frequency
Static Phase Offset; NOTE 1
Bank Skew; NOTE 2, 6
Output Skew; NOTE 3, 6
Cycle-to-Cycle Jitter; 6
FREF = 25MHz
-365
-105
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7
tsl(o) Slew Rate
1
t_L
t /t
RF
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
See Table 7A for notes.
87608AYI
20% to 80%
200
48
www.icst.com/products/hiperclocks.html
Maximum
166.67
160
60
250
170
20
4
10
700
52
Units
MHz
ps
ps
ps
ps
ps
v/ns
ms
ps
%
REV. B MARCH 11, 2005
6