OZ6933 Datasheet, PDF (5/15 Pages) List of Unclassifed Manufacturers – ACPI CardBus Controller

OZ6933
PIN LIST
Bold Text = Normal Default Pin Name
PCI Bus Interface Pins
Pin Name
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
Description
PCI Bus Address Input/Data: These
pins connect to PCI bus signals AD[31:0].
A Bus transaction consists of an address
phase followed by one or more data
phases.
PCI Bus Command/Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the
address phase of a transaction,
C/BE[3:0]# are interpreted as the bus
commands. During the data phase,
C/BE[3:0]# are interpreted as byte
enables. The byte enables are to be valid
for the entirety of each data phase, and
they indicate which bytes in the 32-bit data
path are to carry meaningful data for the
current data phase.
Cycle Frame: This input indicates to the
OZ6933 that a bus transaction is
beginning. While FRAME# is asserted,
data transfers continue. When FRAME#
is de-asserted, the transaction is in its final
phases.
Initiator Ready: This input indicates the
initiating agent’s ability to complete the
current data phase of the transaction.
IRDY# is used in conjunction with TRDY#.
Target Ready: This output indicates
target Agent’s the OZ6933’s ability to
complete the current data phase of the
transaction. TRDY# is used in conjunction
with IRDY#.
Stop: This output indicates the current
target is requesting the master to stop the
current transaction.
Initialization Device Select: This input is
used as chip select during configuration
read and write transactions. This is a
point-to-point signal. IDSEL can be used
as a chip select during configuration read
and write transactions.
Device Select: This output is driven
active LOW when the PCI address is
recognized as supported, thereby acting
as the target for the current PCI cycle.
The Target must respond before timeout
occurs or the cycle will terminate.
Parity Error: The output is driven active
LOW when a data parity error is detected
during a write phase.
Pin Number
TQFP
BGA
4-5, 7-12, 16-
20, 22-24, 38-
43, 45-46, 48-
49, 51-56
E1, E2, F3, F1,
G5, H6, G3,
G2, H2, H1, J1,
J2, J3, J6, K1,
K2, M5, N2,
N1, N3, N6, P1,
P3, N5, P6, R2,
R3, T1, W4,
R6, U5, P7
13, 25, 36, 47 G1, K3, M3, R1
27
K6
29
L1
30
L2
32
L5
15
H5
31
L3
33
L6
Input
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
Type
I/O
Power
Rail
4
Drive
PCI Spec
I/O
4
-
I/O
4
-
I/O
4
-
I/O
4
PCI Spec
I/O
4
PCI Spec
I
4
-
I/O
4
PCI Spec
TO
4
PCI Spec
OZ6933-SF-1.7
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