NT256D64S88ABG Datasheet, PDF (5/15 Pages) List of Unclassifed Manufacturers – 184pin One Bank Unbuffered DDR SDRAM MODULE

NT256D64S88ABG
256MB : 32M x 64
PC2700 Unbuffered DIMM
Serial Presence Detect -- Part 1 of 2
32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
Byte
Description
SPD Entry Value
DDR333
-6
Serial PD Data Entry (Hexadecimal) Note
DDR333
-6
Number of Serial PD Bytes Written during
0
128
80
Production
1 Total Number of Bytes in Serial PD device
256
08
2 Fundamental Memory Type
SDRAM DDR
07
3 Number of Row Addresses on Assembly
13
0D
4 Number of Column Addresses on Assembly
10
0A
5 Number of DIMM Bank
1
01
6 Data Width of Assembly
X64
40
7 Data Width of Assembly (cont’)
X64
00
8 Voltage Interface Level of this Assembly
SSTL 2.5V
04
9 DDR SDRAM Device Cycle Time at CL=2.5
6ns
60
DDR SDRAM Device Access Time from Clock
10
0.7ns
70
at CL=2.5
11 DIMM Configuration Type
Non-Parity
00
12 Refresh Rate/Type
SR/1x(7.8µs)
82
13 Primary DDR SDRAM Width
X8
08
14 Error Checking DDR SDRAM Device Width
N/A
00
DDR SDRAM Device Attr: Min CLK Delay,
15
1 Clock
01
Random Col Access
DDR SDRAM Device Attributes:
16
2,4,8
0E
Burst Length Supported
DDR SDRAM Device Attributes: Number of
17
4
04
Device Banks
DDR SDRAM Device Attributes: CAS Latencies
18
2/2.5
0C
Supported
19 DDR SDRAM Device Attributes: CS Latency
0
01
20 DDR SDRAM Device Attributes: WE Latency
1
02
21 DDR SDRAM Device Attributes:
Differential Clock
20
22 DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23 Minimum Clock Cycle at CL=2
7.5ns
75
Maximum Data Access Time from Clock at
24
0.7ns
70
CL=2
25 Minimum Clock Cycle Time at CL=1
N/A
00
Maximum Data Access Time from Clock at
26
N/A
00
CL=1
27 Minimum Row Precharge Time (tRP)
18ns
48
Minimum Row Active to Row Active delay
28
12ns
30
(tRRD)
29 Minimum RAS to CAS delay (tRCD)
18ns
48
30 Minimum RAS Pulse Width (tRAS)
42ns
2A
31 Module Bank Density
256MB
40
Address and Command Setup Time Before
32
0.75ns
75
Clock
33 Address and Command Hold Time After Clock
0.75ns
75
34 Data Input Setup Time Before Clock
0.45ns
45
35 Data Input Hold Time After Clock
0.45ns
45
36-61 Reserved
Undefined
00
62 SPD Revision
Initial
00
63 Checksum Data
0A
REV 1.1
08/2002
5
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