C8254 Datasheet, PDF (5/6 Pages) List of Unclassifed Manufacturers – PROGRAMMABLE TIMER /COUNTER MEGAFUNCTION

CAST C8254 Megafunction Datasheet
16-Bit Counter
This block contains a 16-bit Binary or BCD presettable synchronous down counter.
8-Bit Status Register
The 8-bit Status Register contains the Control Word Register, the status of the output and null count flag.
When there is a Read-Back Command with STATUSN bit enabled and its counter selected, it will latch present
status information into Status Register. The status format is shown below:
D7
D6
D5 D4 D3 D2 D1 D0
Out Null Count RW1 RW0 M2 M1 M0 BCD
Bits D5 through D0 contain the counter’s programmed Mode. Output bit D7 contains the current state of the
OUT pin. This allows the user to monitor the counter’s output via software. Null Count bit D6 indicates when
the last count written to the counter register has been loaded into the counting element (CE16). The exact
time this happens depends on the Mode of the counter.
8-Bit Output Latch Register
At the time of receiving the Counter Latch Command or Read-Back Command with COUNTN bit enabled, the
selected counter’s output latch latches the count. This count is held in the latch until the CPU reads it or until
the counter is reprogrammed. The count is then unlatched and the OL returns to be transparent of counting
element outputs. The count must be read according to the programmed format. The Counter Latch Command
is ignored before the count is read.
Read Counter
If both the count and the status of a counter are latched, the first read operation of that counter will return
the latched status, regardless of which was latched first. The next one or two reads (depending on whether
the counter is programmed for one or two byte counts) returns the latched count. Subsequent reads return
the unlatched count. If the counter is programmed for two byte counts, it will read the LSB first then the MSB
at the next read cycle.
Verification Methods
The C8254 megafunction’s functionality was verified by means of a proprietary hardware modeler. The same
stimulus was applied to a hardware model that contained the original Intel 82C54 chip, and the results
compared with the megafunction’s simulation output
Device Utilization & Performance
Supported
Family
Cyclone
Stratix
Stratix-II
Device
Tested
EP1C20-6
EP1S20-5
EP2S60-3
Utilization
LEs
Memory Memory bits
524
0
0
524
0
0
536
0
0
Performance
F_max
109 MHz
119 MHz
166 MHz
CAST, Inc.
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