24A01 Datasheet, PDF (5/24 Pages) List of Unclassifed Manufacturers – 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power

FUNCTION DESCRIPTION
I²C-BUS INTERFACE
The TMC 24A01/24A02/24A04/24A08/24A16 supports the I²C-bus serial interface data transmission protocol.
The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines
must be connected to V_CC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight TMC 24A01/24A02 (four
TMC24A04, two for TMC24A08, one for TMC24A16) devices can be connected to the same I²C-bus as
slaves (see Figure 3-6). Both the master and slaves can operate as transmitter or receiver, but the master device
determines which bus operating mode would be active.
VCC VCC
SDA
SCL
Bus Master
(Transmitter/
Receiver)
MCU
Slave 1
TMC24A02
Tx/Rx
A0 A1 A2
Slave 2
TMC 24A02
Tx/Rx
A0 A1 A2
Slave 3
TMC24A02
Tx/Rx
A0 A1 A2
Slave 8
TMC 24A02
Tx/Rx
A0 A1 A2
To VCC or VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
NOTES:
1. The A0 does not affect the device address of the TMC 24A04
2. The A0, A1 do not affect the device address of the TMC 24A08.
3. The A0, A1, and A2 do not affect the device address of the TMC 24A16.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I²C-Bus)
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