WCMA4008C1X Datasheet, PDF (4/10 Pages) List of Unclassifed Manufacturers – 512K x 8 Static RAM

WCMA4008C1X
Switching Characteristics^[4] Over the Operating Range
WCMA4008C1X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
WRITE CYCLE^[7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z^[5]
OE HIGH to High Z^{[5, 6]}
CE LOW to Low Z^[5]
CE HIGH to High Z^{[5, 6]}
CE LOW to Power-Up
CE HIGH to Power-Down
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
10
ns
25
ns
0
ns
70
ns
t_WC
Write Cycle Time
70
ns
t_SCE
CE LOW to Write End
60
ns
t_AW
Address Set-Up to Write End
60
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-Up to Write Start
0
ns
t_PWE
WE Pulse Width
55
ns
t_SD
Data Set-Up to Write End
30
ns
t_HD
t_LZWE
t_HZWE
Data Hold from Write End
WE HIGH to Low Z^[5]
WE LOW to High Z^{[5, 6]}
0
ns
5
ns
25
ns
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 100-pF load capacitance.
5. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
6. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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