WCMA4008C1X Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – 512K x 8 Static RAM

WCMA4008C1X
Features
• Voltage Range
— 4.5V–5.5V
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = f_max
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
Functional Description
The WCMA4008C1X is a high-performance CMOS static
RAM organized as 512K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE), an active
Logic Block Diagram
512K x 8 Static RAM
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location speci-
fied on the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the con-
tents of the memory location specified by the address pins will
appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The WCMA4008C1X is available in a standard 32-pin
450-mil-wide body width SOIC.
A₀
A₁
A₄
A₅
A₆
A₇
A₁₂
A₁₄
A₁₆
A₁₇
CE
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Pin Configuration
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Top View
SOIC
A₁₇ 1
A_{16 2}
A₁₄ 3
A_{12 4}
A₇ 5
A_{6 6}
A_{5 7}
A₄ 8
A_{3 9}
A_{2 10}
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 V_CC
31 A₁₅
30 A₁₈
29 WE
28 _A13
27 _A8
26
25
A₉
A₁₁
24 _OE
23 A₁₀
22 CE
21 I/O7
20 ^I/O₆
19 ^I/O5
18 ^I/O4
17 I/O₃