STC62WV51216 Datasheet, PDF (4/9 Pages) List of Unclassifed Manufacturers – Very Low Power/Voltage CMOS SRAM

STC
„ AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
Output Load
0.5Vcc
CL = 30pF+1TTL
CL = 100pF+1TTL
STC62WV51216
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85^oC )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
CYCLE TIME : 70ns CYCLE TIME : 55ns
Vcc = 2.7~5.5V
Vcc = 3.0~5.5V
MIN. TYP. MAX. MIN. TYP. MAX.
t
AVAX
t
RC
Read Cycle Time
70 -- -- 55 -- --
t
AVQV
t
AA
Address Access Time
-- -- 70 -- -- 55
t
ELQV
t
ACS
Chip Select Access Time
(CE) -- -- 70 -- -- 55
t
BA
t (1)
BA
Data Byte Control Access Time
(LB,UB) --
--
35 --
--
30
t
GLQV
t
OE
Output Enable to Output Valid
-- -- 35 -- -- 30
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE) 10 -- -- 10 -- --
t
BE
t
BE
Data Byte Control to Output Low Z (LB,UB) 5
--
--
5
--
--
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5 -- -- 5 -- --
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE) -- -- 35 -- -- 30
t
BDO
t
BDO
Data Byte Control to Output High Z (LB,UB) -- -- 35 -- -- 30
t
GHQZ
t
OHZ
Output Disable to Output in High Z
-- -- 30 -- -- 25
t
AXOX
t
OH
Data Hold from Address Change
10 -- -- 10 -- --
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-STC62WV51216
4
Revision 2.1
Jan. 2004