MTD655 Datasheet, PDF (4/18 Pages) List of Unclassifed Manufacturers – 5 Port 10M/100M Hub With 2 port Switch

MYSON
TECHNOLOGY
MTD655
1.0 PIN DESCRIPTIONS
MII Port Interface Pins (port0)
Name
RXD0_0
RXD0_1
RXD0_2
RXD0_3
CRS0
RXDV0
RXCLK0
TXEN0
TXD0_0
TXD0_1
TXD0_2
TXD0_3
TXCLK0
Pin Number
19
20
27
28
30
29
15
18
17
16
10
9
12
I/O
Descriptions
I Port0 MII receive data bit_0.
I Port0 MII receive data bit_1.
I Port0 MII receive data bit_2.
I Port0 MII receive data bit_3.
I Port0 MII asynchronous carrier indicator from PHY device.
I Port0 MII synchronous receive data valid signal from PHY device.
I Port0 MII receive clock.
O Port0 MII transmit enable signal.
O Port0 MII transmit data bit_0.
O Port0 MII transmit data bit_1.
O Port0 MII transmit data bit_2.
O Port0 MII transmit data bit_3.
I Port0 MII transmit clock.
Name
CRSDV1
RXD1_0
RXD1_1
TXEN1
TXD1_0
TXD1_1
CRSDV2
RXD2_0
RXD2_1
TXEN2
TXD2_0
TXD2_1
CRSDV3
RXD3_0
RXD3_1
TXEN3
TXD3_0
TXD3_1
CRSDV4
RMII Port Interface Pins (port1 ~port4)
Pin Number
33
37
38
36
35
34
39
43
44
42
41
40
47
51
52
50
49
48
53
I/O
Descriptions
I Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
I Port1 RMII receive data bit_0.
I Port1 RMII receive data bit_1.
O Port1 RMII transmit enable signal.
O Port1 RMII transmit data bit_0.
O Port1 RMII transmit data bit_1.
I Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
I Port2 RMII receive data bit_0.
I Port2 RMII receive data bit_1.
O Port2 RMII transmit enable signal.
O Port2 RMII transmit data bit_0.
O Port2 RMII transmit data bit_1.
I Port3 RMII receive interface signal, CRSDV3 is asserted high when
port3 media is non_idle.
I Port3 RMII receive data bit_0.
I Port3 RMII receive data bit_1.
O Port3 RMII transmit enable signal.
O Port3 RMII transmit data bit_0.
O Port3 RMII transmit data bit_1.
I Port4 RMII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
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MTD655 Revision 2.0 17/03/2000