M11B11664A Datasheet, PDF (4/15 Pages) List of Unclassifed Manufacturers – 64 K x 16 DRAM EDO PAGE MODE

(OLWH07
M11B11664A
CAPACITANCE (Ta = 25 °C , VCC = 5V ± 10%)
PARAMETER
SYMBOL
TYP
Input Capacitance (address)
CI1
-
Input Capacitance ( RAS , CASH , CASL , WE , OE )
CI2
-
Output capacitance (I/O0~I/O15)
CI / O
-
MAX
5
7
10
UNIT
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =5V ± 10%, VSS = 0V) (note 14)
Test Conditions
Input timing reference levels : 0V, 3V
Output reference level : VOL= 0.8V, VOH=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed tT = 2ns
PARAMETER
-25
SYMBOL
MIN MAX
-30
MIN MAX
-35
MIN MAX
-40
MIN MAX
UNIT Notes
Read or Write Cycle Time
tRC
43
55
65
75
ns
Read Write Cycle Time
tRWC 65
85
95
105
ns
EDO-Page-Mode Read or Write Cycle
Time
tPC
10
12
14
16
ns 22
EDO-Page-Mode Read-Write Cycle
Time
tPCM
32
37
42
47
ns 22
Access Time From RAS
tRAC
25
30
35
40
ns
4
Access Time From CAS
tCAC
8
9
10
11 ns 5,20
Access Time From OE
tOAC
8
9
10
11 ns 13,20
Access Time From Column Address
tAA
12
15
18
20 ns
Access Time From CAS Precharge
tACP
14
17
20
22 ns 20
RAS Pulse Width
RAS Pulse Width (EDO Page Mode)
RAS Hold Time
tRAS 25 10,000 30 10,000 35 10,000 40 10,000 ns
tRASC 25 100,000 30 _100,000 35 _100,000 40 _100,000 ns
tRSH
8
9
10
11
ns 25
RAS Precharge Time
tRP
15
20
25
30
ns
CAS Pulse Width
CAS Hold Time
CAS Precharge Time
tCAS 4 10,000 5 _10,000 5 _10,000 6 _10,000 ns 24
tCSH
21
26
30
35
ns 19
tCP
4
4
5
5
ns 6,23
RAS to CAS Delay Time
tRCD 10 17 10 21 10 25 10 29 ns 7,18
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
RAS to Column Address Delay Time
tCRP
5
5
5
5
ns 19
tASR
0
0
0
0
ns
tRAH
5
5
5
5
ns
tRAD 8 13 8 15 8 17 8 20 ns
8
Column Address Setup Time
tASC
0
0
0
0
ns 18
Column Address Hold Time
tCAH
5
5
5
5
Column Address Hold Time (Reference
to RAS )
tAR
22
26
30
34
Column Address to RAS Lead Time
tRAL
12
15
18
20
ns 18
ns
ns
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3
4/15