M11B11664A Datasheet, PDF (12/15 Pages) List of Unclassifed Manufacturers – 64 K x 16 DRAM EDO PAGE MODE

(OLWH07
CBR REFRESH CYCLE
(A0~A7 ; OE = DON’T CARE)
VIH
RAS _VIL
VIH
CASL,CASH _VIL
VOH
I/O _VOL
V IH
WE _VIL
tRP
tRAS
tR PC
tCP
tCS R
tCHR
tRC H
tRS R tRHR
( NOT E1 )
tRP
tR AS
tR PC
tCSR
tCHR
OPEN
tRSR tRHR
M11B11664A
HIDDEN REFRESH CYCLE
WE = HIGH ; OE = LOW
RAS
VIH
VIL
VIH
CASL,CASH _VIL
VIH
ADDR _VIL
VO H
I/O _VOL
VIH
OE _VIL
( RE AD )
t RAS
tRP
tC RP
tRC D
tRSH
tASR
tRAD
tRAH
tAR
t ASC
tRAL
tCAH
ROW
CO LU MN
t RAC
tAA
t CAC
tCLZ
OPEN
tOAC
tORD
(REF RESH)
t RAS
tCHR
VALID DATA
NOTE2
tO FF 1
tO FF
2
OPEN
DON'T CARE
UNDEFINED
Note : 1. tRSR and tRHR are for system design reference only. The WE signal is actually a “don’t care” at RAS time during a CBR
REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other
DRAMs which require WE HIGH at RAS time during a CBR REFRESH.
2. tOFF1 is reference from the rising edge of RAS or CAS , whichever occurs last.
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3
12/15