ICM107 Datasheet, PDF (4/20 Pages) List of Unclassifed Manufacturers – ICM107B Mega pixel Color CMOS image sensor

ICM107B Mega pixel CMOS sensor
Data Sheet Version 1.0 July 2002
1. Preliminary Pin Assignment
Pin #
Name
Class*
Function
14
11
12
13
33
35
31
32
2
1
10
17
8
48
47
46
45
44
43
40
39
38
37
36
3
5
34
15
30,7
29,9
19
18
41,4
CLKSEL
D, I, N
CLKIN
XIN
XOUT
PCLK
OEN
SIF ID
MSSEL
SCL
SDA
POWERDN
RSET
RSTN
DOUT[10]
DOUT[9]
DOUT[8]
DOUT[7]
DOUT[6]
D, I, N
A, I
A, O
D, O
D, I, N
D, I, N
D, I, U
D, I/O
D, I/O
D, I, N
A, I
D, I, U
D, I/O
D, I/O
D, I/O
D, O
D, I/O
DOUT[5]
D, I/O
DOUT[4]
DOUT[3]
DOUT[2]
DOUT[1]
DOUT[0]
D, I/O
D, I/O
D, I/O
D, I/O
D, I/O
HSYNC
VSYNC
FLASH
RAMP
VDDA
GNDA
VDDD
GNDD
VDDK
D, I/O
D, I/O
D, O
A, O
P
P
P
P
P
Clock source selection
0: clocks pass PLL, use XIN (pin 12)
1: bypass PLL, use CLKIN (pin 11)
External clock source; bypass PLL
Crystal oscillator in, or external clock in; if external
clocks used, leave Xout (pin 13) unconnected
Crystal oscillator out
Pixel clock output
Output enable. 0: enable, 1: disable
LSB of SIF slave address
SIF master/slave selection. 0: slave, 1: master
SIF clock
SIF data
Power down control, 0: power down, 1: active
Resistor to ground = 25 KΩ @ 48 MHz main clock,
(or 50KΩ @ 24 MHz main clock)
Chip reset, active low
Data output bit 10
Data output bit 9
Data output bit 8
Data output bit 7
Data output bit 6; if pulled up/down, the initial value
of TIMING_CONTROL_LOW[2] (VSYNC polarity)
is 1/0
Data output bit 5; if pulled up/down, the initial value
of TIMING_CONTROL_LOW[1] (HSYNC polarity)
is 1/0
Data output bit 4; if pulled up/down, the initial value
of AD_IDL[3] (Sub ID) is 1/0
Data output bit 3; if pulled up/down, the initial value
of AD_IDL[2] (Sub ID) is 1/0
Data output bit 2; if pulled up/down, the initial value
of AD_IDL[1] (Sub ID) is 1/0
Data output bit 1; if pulled up/down, the initial value
of AD_IDL[0] (Sub ID) is 1/0
Data output bit 0; if pulled up/down, the
synchronization mode is in master/slave mode which
requires HSYNC and VSYNC operating in
output/input mode
Horizontal sync signal
Vertical sync signal
Flash light control
Analog ramp output
Sensor analog power
Sensor analog ground
Sensor digital power
Sensor digital ground
Digital power
©2000, 2001,2002 IC Media Corporation & IC Media Technology Corp
web site: http://www.ic-media.com/
10/29/2002
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