H4005 Datasheet, PDF (4/6 Pages) List of Unclassifed Manufacturers – ISO 11 784 / 11 785 COMPLIANT READ ONLY CONTACTLESS IDENTIFICATION DEVICE

EM MICROELECTRONIC-MARIN SA
Block Diagram
COIL1
Cres
AC1
FULL WAVE
RECTIFIER
AC2
CLOCK
EXTRACTOR
VDD
Csup
Logic
Clock
SEQUENCER
COIL2
DATA
MODULATOR
VSS
H4005
MEMORY
ARRAY
Serial
Data out
Modulation
Control
DATA
ENCODER
Fig. 4
Functional Description
General
The H4005 is supplied by means of an electromagnetic field
induced on the attached coil. The AC voltage is rectified in order
to provide a DC internal supply voltage. When the DC voltage is
sufficient the chip sends data continuously. When the last bit is
sent, the chip will continue with the first bit until the power goes
off.
Full Wave Rectifier
The AC input induced in the external coil by an incident
magnetic field is rectified by a Graetz bridge. The bridge will limit
the internal DC voltage to avoid malfunction in strong fields.
Clock extractor
One of the coil terminals (COIL1) is used to generate the master
clock for the logic function. The output of the clock extractor
drives a sequencer.
Sequencer
The sequencer provides all necessary signals to address the
memory array and to encode the serial data out. The data rate is
set to 32 clocks per bit.
Data Modulator
The data modulator is controlled by the signal Modulation
Control in order to induce a high current on COIL2 terminal
when this signal is at logic "0". This will affect the magnetic field
according to the data stored in the memory array.
Memory
The memory contains 128 bits laser programmed during
manufacturing according to a customer list of codes. The bits
are read serially in order to control the modulator. The 128 bits
output sequence is repeated continuously until power goes off.
Memory Map
Send bit 1 first
1 11 12
Header
11 bits
Identification code
64 + 8 bits
128 bit pattern ISO 11785
83 84 101 102
128
CRC
Extension
16 + 2 bits 24 + 3 bits
Data Encoder
The data is coded according to the FDX-B scheme. At the
beginning of each bit, a transition will occur. A logic bit "1" will
keep its state for the whole bit duration and a logic bit "0" will
show a transition in the middle of the bit duration (refer to fig. 4).
The FDX-B allows an advance of up to 8 clocks in the ON to
OFF transition. Due to its low power consumption, there is no
difference in performance for the H4005 when implementing a
transition advance. No clock advance is provided on the
standard version.
64 Send first
Fig. 5
National code
Country
Reserved
27 26
17 16 15
21
64 bit pattern Identification code ISO 11784
4