CM8500 Datasheet, PDF (4/13 Pages) List of Unclassifed Manufacturers – 3A BUS TERMINATOR

FUNCTIONAL DESCRIPTION
CM8500
3A BUS TERMINATOR
The CM8500 is a switching regulator that is capable of sinking INPUTS
and sourcing 3A of current without an external heat sink.
The input voltage pins (VCCQ or VIN/2) determine the output
CM8500 uses a standard surface mount PTSSOP and PSOP voltages (VL1 or VL2). In the default mode, when the VIN/2 pin
package with bottom metal exposed and the heat can be
is open, the output voltage is 50% of the VCCQ input.
piped through the bottom of the device and onto the PCB.
If a specific voltage is forced at the VIN/2 pin, the output voltage
follows the voltage at the VIN/2 pin. VCCQ suggested
The CM8500 integrates power MOSFETs that are capable of connecting to VCCQ of memory module for better tracking with
source and sink 3A of current while maintaining excellent
memory VCCQ.
voltage regulation. The output voltage can be regulated within
3% or less by using the external feedback. Separate voltage OTHER SUPPLY VOLTAGES
supply inputs have been added to fit applications with various Several inputs are provided for the supply voltages: PVDD1,
power supplies for the databus and power buses.
PVDD2, VCC1, and VCC2.
OUPUTS
The PVDD1 and PVDD2 provide the power supply to the power
The output voltage pins (VL1, VL2) are tied to the databus, MOSFETs. VCC1 and VCC2 provide the voltage supply to the
address, or clock lines via an external inductor. Output voltage logic section and internal error amplifiers.
is determined by the VCCQ or VIN/2 inputs.
FEEDBACK
The VFB pin is an input that can be used for closed loop
compensation. This input is derived from the voltage output.
AGSEN pin is a contact node of internal resistor divider for
remote sense.
APPLICATIONS
USING THE CM8500 FOR SSTL BUS TERMINATION
Figure 1 is the typical schematic of the CM8500TEVAL that
shows the recommended approach for bus terminating
solutions for SSTL-2 bus. This circuit can be used in PC
memory and Graphics memory applications as shown in
Figure 2 and Figure 3.
Figure 4 shows the PCB layout of the CM8500TEVAL.
Table 1details the key parameters of SSTL_2 specification.
Figure 5 shows two different approach of SSTL_2 Terminated
Output. (Refer to page 8 for detail description.)
2004/06/01 Rev. 1.1
Champion Microelectronic Corporation
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