LM3S6611 Datasheet, PDF (392/477 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX
FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
NEWTX
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
NEWTX
Type
RO
R/W
Reset
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
15.6
MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 375.
392
October 09, 2007
Preliminary