LM3S6611 Datasheet, PDF (379/477 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6611 Microcontroller
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the
interrupt, while writing a 1 enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PHYINTM MDINTM RXERM FOVM TXEMPM TXERM RXINTM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bit/Field
31:7
6
5
4
3
2
1
0
Name
reserved
PHYINTM
MDINTM
RXERM
FOVM
TXEMPM
TXERM
RXINTM
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0x0
1
1
1
1
1
1
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask PHY Interrupt
This bit masks the PHYINT bit in the MACRIS register from being
asserted.
Mask MII Transaction Complete
This bit masks the MDINT bit in the MACRIS register from being
asserted.
Mask Receive Error
This bit masks the RXER bit in the MACRIS register from being asserted.
Mask FIFO Overrrun
This bit masks the FOV bit in the MACRIS register from being asserted.
Mask Transmit FIFO Empty
This bit masks the TXEMP bit in the MACRIS register from being
asserted.
Mask Transmit Error
This bit masks the TXER bit in the MACRIS register from being asserted.
Mask Packet Received
This bit masks the RXINT bit in the MACRIS register from being
asserted.
October 09, 2007
379
Preliminary