M13S128168A Datasheet, PDF (31/48 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128168A
Current State _{CS RAS CAS WE}
Address
Command
H X X XX
DESEL
L H H HX
NOP
L H H L BA
Burst Stop
L H L X BA, CA, A10
RE-FRESHING
L
L
H
H BA, RA
READ/WRITE
Active
L
L
H
L BA, A10
PRE / PREA
L
L
L
HX
Refresh
L
L
L
L Op-Code Mode-Add MRS
H X X XX
DESEL
L H H HX
NOP
L H H L BA
MODE
L H L X BA, CA, A10
REGISTER
SETTING
L
L
H
H BA, RA
L
L
H
L BA, A10
Burst Stop
READ / WRITE
Active
PRE / PREA
L
L
L
HX
Refresh
L
L
L
L Op-Code Mode-Add MRS
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Action
NOP (Idle after t_RP)
NOP (Idle after t_RP)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after t_RP)
NOP (Idle after t_RP)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be
performed.
7. Refer to “Read with Auto Precharge: for more detailed information.
ILLEGAL = Device operation and / or data integrity are not guaranteed.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2006
Revision : 1.5
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