LM3S601_06 Datasheet, PDF (31/397 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S601 Data Sheet
1.4.5.3
1.4.6
1.4.6.1
1.4.6.2
1.4.7
1.4.7.1
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock
(RTC).
When configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or Real-Time
Clock (RTC). When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
Watchdog Timer (Section 10 on page 179)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first
time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
Memory Peripherals
The Stellaris controllers offer both SRAM and Flash memory.
SRAM (Section 7.2.1 on page 95)
The LM3S601 static random access memory (SRAM) controller supports 8 KB SRAM. The
internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled
processor, certain regions in the memory map (SRAM and peripheral space) can use address
aliases to access individual bits in a single, atomic operation.
Flash (Section 7.2.2 on page 96)
The LM3S601 Flash controller supports 32 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of
code protection. Read-only blocks cannot be erased or programmed, protecting the contents of
those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can
only be read by the controller instruction fetch mechanism, protecting the contents of those blocks
from being read by either the controller or by a debugger.
Additional Features
Memory Map (Section 3 on page 37)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S601 controller can be found on page 37. Register addresses are given as a hexadecimal
increment, relative to the module’s base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
October 8, 2006
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Preliminary