BT8110 Datasheet, PDF (31/84 Pages) List of Unclassifed Manufacturers – High-Capacity ADPCM Processor

Bt8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.3 Direct Framer Interface Operation
2.3 Direct Framer Interface Operation
The direct framer interface operation modes are intended for voice compression
and storage applications such as voice mail, voice message store and forward, or
voice response. For more details, see the Speech Compression Interface
application notes, Appendix B and C of this specification.
2.3.1 T1 Framer Interface
In this configuration, address 0x40 must be set to a value of 0x14 to properly set
the Bt8110/8110B mode. The per-channel control registers given in Table 3-3
must be configured for the appropriate code selection, coding type, and
transparency. The Bt8110 allows only 56 kbit/s data rate in transparent mode. The
Bt8110B operates at a full 64 kbit/s data rate. The full-rate PCM signals are serial
and are connected directly to the SERIAL_IN and SERIAL_OUT pins.
In this application, the PSIGEN input must be held low, thus enabling the
parallel interface for the ADPCM inputs PSIG[7:0] and outputs D[7:0]. The
ADPCM inputs and outputs are timed by the signal ADPCM_STB. The ADPCM
input to the Bt8110/8110B is applied to the parallel input PSIG[7:3] with the
most significant bit at PSIG[7]. The ADPCM output is obtained from the Parallel
Signal Output Bus D[7:0] with the most significant bit at D[7].
The Bt8110/8110B interfaces to a T1 framer, which is used to transmit and
receive a digital line at the 1.544 Mbit/s rate. The slip buffer of the T1 framer
frame-synchronizes the receive signal to the transmit signal so that the
Bt8110/8110B can operate synchronously on both signals.
The ADPCM input data must be valid at the positive edge of ADPCM_STB;
the ADPCM output data is valid at the positive edge. Due to the processing delay
of the Bt8110/8110B, there is a five-channel offset between the timing of the
ADPCM input and PCM output.
The ADPCM output is always 5 bits (for 40 kbit/s coding and for all
embedded codes) or less. The ADPCM input includes up to 5 ADPCM input bits
and 2 bits to indicate the number of bits in the decoder input when embedded
encoding is used. On the Bt8110 only, the input to PSIG[0], the least significant
bit, must be left open or held at a logic low level (this pin has an internal
pull-down resistor).
The 6.144 MHz clock is obtained by internally dividing and gapping the
12.352 MHz input clock to the Bt8110. The required 12.352 MHz signal source
should be phase-locked to incoming PCM data. A complete implementation of a
48-channel T1 speech compression interface utilizing the Conexant Bt8300 Dual
T1-Framer and the Bt8110/8110B is detailed in Appendix B, T1 Speech
Compression Interface.
100060C
Conexant
2-11