BT8110 Datasheet, PDF (11/84 Pages) List of Unclassifed Manufacturers – High-Capacity ADPCM Processor

Bt8110/8110B
High-Capacity ADPCM Processor
1.0 Product Description
1.1 Channel Capacity and Configuration Modes
1.1.2 Embedded Coding
The Bt8110/8110B has the capability to provide embedded coding according to
ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. This coding
technique allows the encoding to be performed with 5 bits of encoding
information, and the decoding to be done with anywhere from 2 to 5 input bits.
The coding algorithm is defined so that although the coding distortion increases
as the number of bits at the decoder decreases, the encoder and the decoder will
remain synchronized.
The Bt8110/8110B is designed so that embedded coding is enabled by the
ROM code selected. Along with four different standard (non-embedded) ADPCM
codes, two embedded codes can be provided with a 64 K ROM and up to six
different embedded codes, with eight different standard (non-embedded) codes,
can be provided with a 128 K ROM. The encoder always provides the maximum
number of bits (up to 5) defined by the code selected. The decoder requires up to
5 ADPCM bits and a 2-bit encoded input that indicates how many bits are present
at the decoder input. This input signal is applied to bits 1 and 2 of the parallel
input bus. If embedded coding is not in use, bits 1 and 2 should be connected to
ground.
1.1.3 Control Mode
Each channel has four sets of per-channel control inputs. These are for selecting
the PCM coding law (A-law or µ-law), selecting transparent operation, selecting
the RESET function of the ADPCM coding algorithm, and selecting which of 14
codes (six codes for a 64 K ROM) is used for encoding or decoding.
The microprocessor mode is selected by setting input MICREN high. The
microprocessor can address 65 different registers. There is a control register for
each of the encoder and decoder channel operations and a mode control register
that sets the operating mode of the Bt8110/8110B.
100060C
Conexant
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