HM17CM4096 Datasheet, PDF (30/67 Pages) List of Unclassifed Manufacturers – 128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM

HM17CM4096
When display RAM is accessed by 16 bit data width, the weight of each data bit is dependent on
the status of SWAP register and REF register, the same method as 8 bit access.
12 bit data are extracted from 16 bit address, and then transmitted to gradation palettes.
At 8 bit – 4096 gradation mode , two 8 bit address map is used at display.
More detail information, please refer to bit assign table.
• ACCESS when (REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
i=0~127
Pa^„ let^Âte ^† Aj ^‡ Aj
Palette Bj
Palette Cj
Gradation palette
j=0~15
Gradation
control circuit.
0 0 0 0 1 0 1 0 1 1 1 1 Display RAM data
LSB
MSB LSB
MSB LSB
MSB
000010101111
D₁ D₂ D₃ D₄ D₇ D₀ D₁ D₂ D₄ D₅ D₆ D₇
X address :n_H
X address :n+1_H
notice) internal access X address :n_H~FF_H (access when REF=”0”)
:FF_H~n_H (access when REF=”1”)
• ACCESS when (REF, SWAP)=(0, 1) or (1, 0)
SEGAi
SEGBi
SEGCi
CPU access data
i=0~127
Pa^„ let^Âte ^† Cj^‡ Aj
Palette Bj
Palette Aj
Gradation palette
j=0~15
Gradation
control circuit.
1 1 1 1 0 1 0 1 0 0 0 0 Display RAM data
MSB
LSB MSB
LSB MSB
LSB
000010101111
D₁ D₂ D₃ D₄ D₇ D₀ D₁ D₂ D₄ D₅ D₆ D₇
X address :n_H
X address :n+1_H
notice) internal access X address :n_H~FF_H (access when REF=”0”)
:FF_H~n_H (access when REF=”1”)
CPU access data
- 30 -