VDD8616A8A Datasheet, PDF (3/9 Pages) List of Unclassifed Manufacturers – Double Data Rate SDRAM

V-Data
VDD8616A8A
Pin Description
PIN
CK, /CK
CKE
NAME
System Clock
Clock Enable
/CS Chip Select
A0~A12 Address
BS0~BS1 Banks Select
DQ0~DQ15 Data
/RAS Row Address Strobe
/CAS Column Address Strobe
/WE Write Enable
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
VREF Reference Voltage
NC
No Connection
FUNCTION
Differential clock input.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS
low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
Reference voltage for inputs for SSTL interface.
This pin is recommended to be left No Connection on the device.
Block Diagram
CK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
Mode
Register
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank3
Bank2
Bank1
Bank0
Amplifier
Column Decoder
Data Control Circuit
DQM
DQS
DQ0~DQn
Rev 2 April, 2002
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