PD63000 Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – PoE Microcontroller Unit

PD63000
8-bit PoE Microcontroller Unit
Pin Functionality _______________________________________________
PIN PIN NAME PIN TYPE
1. Reset
Digital input
2. PTG7
3. PTC0/TxD2 Digital I/O
4. PTC1/RxD2 Digital I/O
5. PTC2/SDA Digital I/O
6. PTC3/SCL Digital I/O
7. PTC4
Digital I/O
8. PTC5
Digital I/O
9. PTC6
Digital I/O
10 PTC7
Digital I/O
11 PTF2
12 PTF3
13 PTF4
14 PTE0/TxD1 Digital I/O
15 PTE1/RxD1 Digital I/O
16 IRQ
Digital input
17 PTE2/SS Digital I/O
18 PTE3/MISO Digital I/O
19 PTE4/MOSI Digital I/O
20 PTE5/SPSCK Digital I/O
21 PTE6
Digital I/O
22 PTE7
Digital I/O
23 VSS
Digital
24 VDD
Digital
25 PTD0/TPM1
26 PTD1/TPM1
27 PTD2/TPM1
28 PTD3/TPM2
29 PTD4/TPM2 Digital I/O
30 PTD5/TPM2 Digital I/O
31 PTD6/TPM2 Digital I/O
32 PTD7/TPM2 Digital I/O
33 PTB0/AD0 A/D input
PIN DESCRIPTION
xRESET_IN (1)
SDA
SCL
TX_3_3_V
RX_3_3_V
xInt_in
MISO
MOSI
SCK
xDISABLE_PORTS
D (ground)
3_3VCPU
Shorted to pin 28
Shorted to pin 25
xSPI_CS0
xSPI_CS1
xSPI_CS2
xSPI_CS3
PIN PIN NAME PIN TYPE
PIN DESCRIPTION
34 PTB1/AD1 A/D input HW VER
35 PTB2/AD2 A/D input
36 PTB3/AD3 A/D input I2C_Init_E
37 PTB4/AD4 A/D input GND_Analog_CPU
38 PTB5/AD5 A/D input
39 PTB6/AD6 A/D input
40 PTB7/AD7 A/D input
41 VREFH
A/D ref.
VREFH
42 VREFL
A/D ref.
GND_Analog_CPU
43 PTF5
44 PTF6
45 PTF7
46 PTA0/KBIP0 Digital I/O xASIC_RESET (1)
47 PTA1/KBIP1 Digital I/O xDISABLE_PORTS_TO_ASIC (1)
48 PTA2/KBIP2 A/D input Power Good PG3 (2)
49 PTA3/KBIP3 A/D input Power Good PG2 (2)
50 PTA4/KBIP4 A/D input Power Good PG1 (2)
51 PTA5/KBIP5 A/D input
52 PTA6/KBIP6
53 PTA7/KBIP7
54 PTF0
55 PTF1
56 VDDAD Analog
VDDAD
57 VSSAD
Analog
GND_Analog_CPU
58 PTG0/BKGD/ Digital I/O
59 PTG1/XTAL Resonator/o XTAL
60 PTG2/EXTAL Resonator/o EXTAL
61 PTG3
Digital I/O
62 PTG4
Digital I/O
63 PTG5
Digital output xInt_Out (future use)
64 PTG6
Digital I/O SELF RESET
(1). Upon receiving an active low reset level via pin 1 (xRESET_IN) from the switch host, the PD63000 MCU immediately disables all
PoE Manager (PD64012) output ports. The MCU does this using the xDISABLE_PORTS_TO_ASIC signal (pin 47). During this
process, the PoE Managers are still actively operational, although their ports are disabled. Once the active low is released, the MCU
performs a software reboot. After the reboot, the MCU sends a reset to all PoE Managers, via pin 46 (xASIC_RESET).
(2) Refer to Tech Note TN-113 for information on power management.
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06-0008-058(Rev. 1.4) / 10 March 2004
© PowerDsine 2004
Information in this document subject
to change without prior notice.