NT3882 Datasheet, PDF (3/9 Pages) List of Unclassifed Manufacturers – Dot Matrix LCD 40-Channel Driver

NT3882
Pin and Pad Descriptions
Pin No.
Pad No. Designation I/O External Connection
Description
2- 24,
27 - 32,
52 - 57,
59 - 63
27 - 32,
2 - 24,
52 - 57,
59 - 63
S29 - S7,
S6 - S1,
S40 - S35,
S30 - S34
O LCD panel
Segment signal output pins
25
25
VDD
P Power supply
Power for logic circuits
34
34
CL1
I Controller
Clock to latch serial data
35
35
CL2
I Controller
Clock to shift serial data
36
36
GND
P Power Supply
0V
37
37
DL1
I Controlleror NT3882 Data input of 1 - 20 bits from controller
38
38
DR1
O NT3882
Data output of 20 bit shift register
39
39
DL2
I Controlleror NT3882 Data input of 21 - 40 bits from controller
40
40
DR2
O NT3882
Data output of 40 bit shift register
42
42
M
I Controller
Alternate signal for LCD drivers
46, 48, 51 46, 48, 51 VEE, V3, V2
P Power Supply
Power for LCD drivers
1, 26, 33, 41,
43 - 45, 47,
-
49, 50, 58,
64
NC
--
No connection
Functional Description
NT3882 is a dot matrix LCD segment driver LSI. It
operates with the controller, such as NT3881C/D, and/or
another segment driver LSI NT3882. NT3882 receives
serial data from the controller or another NT3882,
converts it to parallel data and then supplies the LCD
driving waveforms to the LCD panel.
1. CL1
This signal is used for latching the shift register contents.
When CL1 is set at high, the shift register contents are
transferred to the 40-bit 4level LCD driver. When CL1 is
set at low, the last display output data (S1 to S40) is
held.
2. CL2
Clock pulse inputs for the two 20-bit shift registers. The
data is shifted to a 40-bit latch at the falling edge of CL2.
The clock singal CL2 must be active when operating to
refresh shift registers' contents.
3. DL1
The 1 - 20 bit data from LCD controller is fed into the
first 20-bit shift register through DL1.
4. DR1
The 20th bit data of first 20-bit shift register output from
DR1. The data shifted out from DR1 after 20 bit delay
are synchronized with the clock pulse (CL2). By
connecting DR1 to DL2, two 20-bit shift registers can be
cascaded to one 40-bit shift register.
5. DL2
The 21 - 40 bit data from the LCD controller is fed into
the second 20-bit shift register through DL2.
6. DR2
The 40th bit data of the second 20-bit shift register
output is from DR2. The data shifted out from DR2 after
a 20-bit delay is synchronized with the clock pulse (CL2).
By connecting DR2 to the next NT3882 DL1, the cascade
construction is obtained to drive a wider LCD panel.
7. S1 to S40
These 40 bits represent the 40 data bits in the 40-bit
latch. One of VDD, V2, V3 and VEE is selected as a LCD
driving voltage source according to the combination of
latched data level and the alternate signal (M).
3