NP3700 Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – 5-Gbps Network Processor with Integrated Traffic Manager

nP3700
5-Gbps Network Processor with Integrated Traffic Manager
Product Brief
PB37xx / V0.92 / 053003
nPcore Architecture
AMCC's software programmable
nPcores are built from the ground up for
both packet- and cell-based networking
data-plane operations. The nP3700
supports 5-Gbps full-duplex operation
utilizing a cluster of three nPcores. Each
nPcore has 24 separate tasks, yielding a
total of 72, which are all available for
either ingress or egress processing. The
nPcores implement zero-cycle task
switching and zero-cycle branching for
enhanced performance.
The nPcores are surrounded by on-chip
coprocessing engines to accelerate
sophisticated network processing
functions, such as packet classification,
route and context searching, statistics
gathering, metering, policing, and packet
transformations. The nPcores, in
combination with these on-chip
coprocessing engines, implement
Network Instruction Set Computing
(NISC) Architecture. This NISC
architecture dramatically reduces the
number of lines of code required to
implement many advanced networking
tasks. A key addition to the fifth
generation of NISC architecture is the
exception channel processing that
provides flexibility in handling packets
that require increased processing time.
This exception channel handles special
packets through a secondary path,
without affecting the deterministic line-
rate performance of the regular packets
in the primary path. Another key addition
to the fifth generation architecture is the
Channel Service Memory that enables
deep channelization in the line interfaces
at all packet sizes and can handle very
large bursts in the incoming traffic
without affecting line rate performance.
Single-Stage, Single-Image
Programming
AMCC's nPcore architecture implements
a simple single-stage programming
model. In this model each cell or packet
is processed in its entirety, from start to
finish, by a single task in a single
nPcore. With this single-stage model,
the entire data flow algorithm can be
created as a single complete software
program, just as it would be on a non-
multiprocessor system, allowing the
same program image to be executed
identically by each task on each nPcore.
This approach greatly simplifies
programming while optimizing
performance.
Traffic Management
The traffic management block in the
nP3700 leverages AMCC’s expertise
and technology from the nPX5700 family
of traffic managers.
The nP3700 family implements a
hierarchical scheduling architecture to
provide multiple levels of bandwidth
provisioning and per-subscriber
guarantees. This hierarchy consists of
four logical levels: flow, pipe, subport
and port. Minimum and maximum
bandwidth control can be configured on
multiple levels. WFQ and Strict Priority
scheduling algorithms are also
implemented by the traffic management
block. For ATM applications, non-real-
time and real-time CBR and VBR
connections can be configured for a
desired subset of flows.
Input Admission Control
Sophisticated cell and packet admission
controls are configurable in the nP3700.
This includes execution of standard
discard mechanisms such as WRED,
EPD, and TPD in hardware or the option
to perform variations in software.
MISSION^TM — Multi-Service
Internetworking Solution
The nP3700, combined with AMCC’s
Evros (S1208) and Tigris (S4811) chips,
provides a cost-effective and highly
flexible multi-service solution. This
solution, called MISSION, combines
state-of-the-art framer, HDLC, and
flexible nP⁵ technology with modular
internetworking software, enabling the
development of single multiprotocol
solutions in place of multiple single-
protocol solutions. The MISSION
architecture provides equipment vendors
with solutions that enable their
customers to save on both capital and
operational expenditures (CapEx/OpEx).
MISSION Software
At the core of the MISSION value
proposition is software that implements a
wide variety of protocols on the chip set
and enables flexible potential additions
to these base software features. AMCC
provides integrated drivers for Evros,
Tigris, and nP3700, and extensive
offerings for the programmable nP3700
Integrated Network Processors,
including both rich off-the-shelf
application software and a complete
development environment for extending
this application base if desired.
The MISSION application software
includes ready-to-use Multi-Service
Switching software – ATM UNI/NNI,
Inverse Multiplexing over ATM (IMA),
Multi-Link Frame Relay (ML-FR), Multi-
Link PPP (ML-PPP), Frame Relay
Interworking (FRIWF) and MPLS Martini
encapsulation – as well as OEM
customer-extensible libraries for the
hardware-resident aspects of higher
layer applications such as IPv4 and IPv6
routing, and Layer 2 packet switching.
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