NP3700 Datasheet, PDF (2/4 Pages) List of Unclassifed Manufacturers – 5-Gbps Network Processor with Integrated Traffic Manager

Product Brief
PB37xx / V0.92 / 053003
nP3700
5-Gbps Network Processor with Integrated Traffic Manager
nP3700 Family Highlights
Interfaces
• Line Interfaces – cell and packet
nP3700
SPI-3
2
GE SPI-4.2
1
1
• Support for Deep Channelization: for
OC-1s, T3/E3s, T1/E1s, etc.
• Fabric Interface: OIF SPI-4 Phase 2
- 800 MHz
• External Memory Interfaces:
RLDRAM II memory controllers
- Payload Memory – 2 banks of 36-bit
RLDRAM II or DDR SDRAM
operating at up to 250 MHz
(32 Gbps with ECC)
- Context Memory:
2 banks of 36-bit RLDRAM II or
DDR SRAM operating at up to
250 MHz (32 Gbps with ECC)
- Channel Service Memory:
One bank of 36-bit QDR-II SRAM
operating at up to 250 MHz
- Flow Database Memory:
Two banks of 18-bit QDR-II SRAM
operating at up to 250 MHz
• CPU Interfaces: PowerPC and
Gigabit Ethernet
• External Search Interface
- Compliant with NPF
- Backward compatibility mode with
existing TCAMs
• Debug port
• JTAG port
High Performance nPcores
• 3 nPCores at 700 MHz
Integrated Coprocessors
• Policy Engine for efficient packet
classification
• Special Purpose Unit (SPU) for per-
flow policing
• Hashing Unit
• On-Chip Debugger (OCD)
Integrated Traffic Manager
• Hierarchical Traffic Manager with
fine-grained flow-based traffic
management
• Leverages field-proven nPX5710 and
nPX5720 technology
SPI3/UT3
SPI3/UT3
GE
(Line/CPU)
18
36 36
36 36
NPF(QDR) QDR
DRAM/SRAM
Scratch
Pad
Cache
SPU
Memory Access Unit
Hash
Engine
Policy
Engine
nPcores
3 cores @ 700 MHz
Packet Transform
Engine
Channel
buffers
CPU Interface
PPC
Debug
nP3700 Block Diagram
36 36
DRAM
Traffic
Manager
Queuing
&
Scheduling
(Switch
Fabric)
JTAG
SPI4.2
2
Empowering Intelligent Wide Area Networks