ES3880 Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – Video CD MPEG Processor

ES3880 PRODUCT BRIEF
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES3880.
Table 1 ES3880 Pin Descriptions List
Name
Number
I/O
Definition
VDD
1, 31, 51
I 3.3V power supply.
RAS#
2
O Row address strobe.
DWE#
3
O DRAM write enable.
DA[8:0]
12:4
O DRAM multiplexed row and column address bus.
DBUS[15:0]
28:13
I/O DRAM data bus.
RESET#
29
I System reset.
VSS
30, 50, 80, 100 I Ground.
YUV[7:0]
39:32
O YUV[7:0] 8-bit video data bus.
VSYNC
40
I/O Vertical sync.
HSYNC
41
I/O Horizontal sync.
CPUCLK
42
I RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00 to bypass
PLL.
PCLK2X
43
I/O Doubled 54 MHz pixel clock.
PCLK
44
I/O 27 MHz pixel clock.
AUX[7:0]
54:52, 49:45 I/O Auxiliary control pins 7:0. AUX0 and AUX1 are open collectors.
LD[7:0]
62:55
I/O RISC interface data bus.
LWR#
63
O RISC interface write enable.
LOE#
64
O RISC interface output enable.
LCS[3,1,0]#
65, 66, 67
O RISC interface chip select.
LA[17:0]
87:82, 79:68
O RISC interface address bus.
VPP
81
I 5.0V power supply.
ACLK
88
I/O Master clock for external audio DAC.
AOUT
O Audio interface serial data output when selected.
I System and DSCK output clock frequency selection at reset time. The matrix below lists
the available clock frequencies and their respective PLL bit settings.
SEL_PLL0
89
SEL_PLL1
0
0
1
1
SEL_PLL0
0
1
0
1
DCLK
Bypass PLL (input mode)
54 MHz (output mode) Default
67.5 MHz (output mode)
81.0 MHz (output mode)
ATCLK
ATFS
SEL_PLL1
DA9
DOE#
AIN
ARCLK
ARFS
TDMCLK
90
I/O Audio transmit bit clock.
O Audio transmit frame sync.
91
I Refer to the description and matrix for SEL_PLL0 pin 89.
92
O DRAM multiplexed row and column address line 9.
O DRAM output enable.
93
I Audio serial data input.
94
I Audio receive bit clock.
95
I Audio receive frame sync.
96
I TDM serial clock.
ESS Technology, Inc.
SAM0191-052901
3