ES1988 Datasheet, PDF (3/6 Pages) List of Unclassifed Manufacturers – PCI Audio-Modem Accelerator Product Brief

ES1988 PRODUCT BRIEF
PIN DESCRIPTION
Table 1 lists the ES1988 pin descriptions
.
Table 1 ES1988 Pin Descriptions
Names
Pin Numbers
I/O
C/BE[3:0]#
1, 13, 20, 30
I/O
IDSEL
I
R0#
I
SPDIFO
2
O
PCREQ#
O
GND
AD[31:0]
VCC
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
CLKRUN#
ECS
GD[0]
GD[1]
EDOUT
GD[2]
EDIN
VOLUP#
3, 21, 40, 89
I
4:11, 22:29,
I/O
31:38, 93:100
12, 41, 90
I
14
I/O
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
I/O
39
O
42
I/O
I/O
43
O
I/O
I
44
I
Descriptions
PCI command/byte enable. During address phase of a transaction, these pins define the bus
command. During data phase, these pins define the byte enable.
ID select. When pin 2 is configured as a multifunction pin (see pin 2 note), IDSEL is selected
internally to AD24.
PCI bus request 0 input from external PCI master device. RO# is enabled by setting the PCIx2
arbiter bit PCI 58h [0] = 1. Select RO# from pin 2 by setting PCI 58h [10] = 1, and pin 2 must be
configured as a multifunction pin. Either pin 2 or pin 52 may be used for R0#.
S/PDIF output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 2 by setting
PCI 58h [1] = 1, and pin 2 must be configured as a multifunction pin. Either pin 2 or pin 54 may
be used for SPDIFO.
PC/PCI request output. Enable PCREQ# by setting PCI 50h [10:8] = 010. Pin 53 is used as
PCREQ# when configured as an audio-only device. PCREQ# can only be used from pin 2 when
the ES1988 is configured as a multifunction device (see pin 60 note). Pin 2 must be configured
as a multifunction pin.
Digital ground.
Address and data lines from the PCI bus.
Digital supply voltage, 3.3V.
Cycle frame.
Initiator ready.
Target ready.
Device select.
Stop transaction.
Parity.
Input/output for PCI Clock status and an output to start or accelerate clock function by enabling
PCI 52h [11] = 1.
Chip select output to EEPROM chip select input. ECS is active after power-on reset and goes
inactive automatically after EEPROM cycle is complete.
Game port data input/output.
Game port data input/output.
Data output to EEPROM data input. EDOUT goes active after power-on reset and goes inactive
automatically after EEPROM cycle is complete.
Game port data input/output.
Data input from EEPROM data output. EDIN goes active after power-on reset and goes inactive
automatically after EEPROM cycle is complete.
Hardware volume control (volume up). Used in combination with pin 45 (VOLDN#). Hardware
volume control is enabled by setting PCI 52 [7] = 1. Pins 44:45 are selected for hardware volume
control by setting PCI 52h [5] = 1. Pins 53:54 may also be used for hardware volume control.
ESS Technology, Inc.
SAM0368-030601
3